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ST7687A
128RGB x 128 dot 65K Color with Frame Memory Single-Chip CSTN Controller/Driver
Datasheet
Version 1.0 2009/12
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
ST7687A
LIST OF CONTENT LIST OF CONTENT ........................................................................................2 LIST OF FIGURES..........................................................................................6 LIST OF TABLES ...........................................................................................7 1 INTRODUCTION .......................................................................................8 2 FEATURES ...............................................................................................9 3 PAD ARRANGEMENT (COG).................................................................10 4 PAD CENTER COORDINATES............................................................... 11 5 BLOCK DIAGRAM..................................................................................21 6 PIN DESCRIPTION .................................................................................22
6.1 6.2 6.3 6.4 6.5 Power Supply.................................................................................................... 22 LCD Power Supply Pins.................................................................................... 23 System Control ................................................................................................. 24 Microprocessor Interface .................................................................................. 25 LCD Driver Outputs........................................................................................... 27 Microprocessor Interface .................................................................................. 29 Selecting Parallel / Serial Interface ................................................................... 30
7.2.1 7.2.2 7.2.3 8-bit or 16-bit Parallel Interface ................................................................................... 30 8- and 9-bit Serial Interface .......................................................................................... 32 8-bit and 9-bit Serial Interface Data Color Coding..................................................... 35
7
FUNCTIONAL DESCRIPTION ................................................................29
7.1 7.2
7.3 7.4
Access to DDRAM and Internal Registers ........................................................ 36 Display Data RAM (DDRAM) ............................................................................ 37
7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 DDRAM........................................................................................................................... 37 Address Control............................................................................................................ 37 I/O Buffer Circuit ........................................................................................................... 40 Scroll Address Circuit .................................................................................................. 40 Display data Latch Circuit ............................................................................................ 40 Normal Display On or Partial Mode On, Vertical Scroll Off ...................................... 40 Vertical Scroll/Rolling Scroll ........................................................................................ 41
Rolling Scroll ................................................................................................................ 41 Vertical Scroll Example ............................................................................................... 42
7.4.7.1 7.4.7.2
7.4.8
Tearing Effect Output Line ........................................................................................... 44
Tearing Effect Line Modes .......................................................................................... 44 Tearing Effect Line Timing .......................................................................................... 45
7.4.8.1 7.4.8.2
7.5 7.6 Ver. 1.0
Gray-Scale Display ........................................................................................... 46 Oscillation circuit............................................................................................... 46 2/191 2009/12
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7.7 7.8 Display Timing Generator Circuit ...................................................................... 47 POWER LEVEL DEFINITION........................................................................... 48
7.8.1 7.8.2 Power ON/OFF SEQUENCE ......................................................................................... 48 Power Levels ................................................................................................................. 49
7.9
Liquid Crystal Driver Power Circuit ................................................................... 50
7.9.1 Voltage Regulator Circuits ........................................................................................... 50
Set V0 (Temperatue = 24)......................................................................................... 50 Set V0 With Temperature Compensation................................................................... 52 V0 fine tuning ............................................................................................................... 54 7.9.1.1 7.9.1.2 7.9.1.3
7.9.2 7.9.3
Voltage Follower Circuits ............................................................................................. 54 PROM Setting Flow....................................................................................................... 54
7.10
Frequency Temperature Gradient Compensation Coefficient ........................... 55 Instruction Table................................................................................................ 56
8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 8.1.13 8.1.14 8.1.15 8.1.16 8.1.17 8.1.18 8.1.19 8.1.20 8.1.21 8.1.22 8.1.23 8.1.24 NOP (00h)....................................................................................................................... 61 SWRESET: Software Reset (01h)................................................................................. 62 RDDST: Read Display Status (09h).............................................................................. 63 RDDPM: Read Display Power Mode (0Ah) ................................................................. 65 RDDMADCTR: Read Display MADCTR (0Bh)............................................................. 67 RDDCOLMOD: Read Display Pixel Format (0Ch) ...................................................... 69 RDDIM: Read Display Image Mode (0Dh) ................................................................... 71 RDDSM: Read Display Signal Mode (0Eh).................................................................. 73 SLPIN: Sleep In (10h).................................................................................................... 75 SLPOUT: Sleep Out (11h) ............................................................................................. 76 PTLON: Partial Display Mode On (12h)....................................................................... 78 NORON: Normal Display Mode On (13h) .................................................................... 79 INVOFF: Display Inversion Off (20h)........................................................................... 80 INVON: Display Inversion On (21h)............................................................................. 81 APOFF: All Pixels Off (22h) (Only for Test Purposes)............................................... 83 APON: All Pixels On (23h) (Only for Test Purposes) ................................................. 85 WRCNTR: Write Contrast (25h) ................................................................................... 87 DISPOFF: Display Off (28h) ......................................................................................... 88 DISPON: Display On (29h)............................................................................................ 90 CASET: Column Address Set (2Ah) ............................................................................ 92 RASET: Row Address Set (2Bh) .................................................................................. 94 RAMWR: Memory Write (2Ch)...................................................................................... 96 RAMRD: Memory Read (2EH) ...................................................................................... 98 PTLAR: Partial Area (30h) .......................................................................................... 100
8
INSTRUCTIONS......................................................................................56
8.1
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8.1.25 8.1.26 8.1.27 8.1.28 8.1.29 8.1.30 8.1.31 8.1.32 8.1.33 8.1.34 8.1.35 8.1.36 8.1.37 8.1.38 8.1.39 8.1.40 8.1.41 8.1.42 8.1.43 8.1.44 8.1.45 8.1.46 8.1.47 8.1.48 8.1.49 8.1.50 8.1.51 8.1.52 8.1.53 8.1.54 8.1.55 8.1.56 8.1.57 8.1.58 8.1.59 8.1.60 8.1.61 8.1.62 SCRLAR: Scroll Area (33h) ........................................................................................ 103 TEOFF: Tearing Effect Line OFF (34h) ...................................................................... 106 TEON: Tearing Effect Line ON (35h) ......................................................................... 107 MADCTR: Memory Data Access Control (36h)......................................................... 109 VSCSAD: Vertical Scroll Start Address of RAM (37h) ............................................. 111 IDMOFF: Idle Mode Off (38h)...................................................................................... 113 IDMON: Idle Mode On (39h)........................................................................................ 114 COLMOD: Interface Pixel Format (3Ah).................................................................... 116 RDID: Read ID Value (DAh) ........................................................................................ 118 DutySet: Display Duty setting (B0H)......................................................................... 119 FirstCom: First Com. Page address (B1H) ............................................................... 121 OscDiv: FOSC Divider (B3H)...................................................................................... 123 NLInvSet: N-Line control (B5H) ................................................................................. 124 ComScanDir: Com/Seg Scan Direction for glass layout (B7H).............................. 125 RMWIN: Read Modify Write control in (B8H)............................................................ 126 RMWOUT: Read Modify Write control out (B9H)...................................................... 127 DispCompStep: Display Compensation Step (BDH) ............................................... 128 VopSet: Vop set (C0H) ................................................................................................ 129 VopOfsetInc: Vop Increase 1 (C1H) ........................................................................... 130 VopOfsetDec: Vop Decrease 1 (C2H) ........................................................................ 131 BiasSel: Bias Selection (C3H) ................................................................................... 133 BstPmpXSel: Booster Setting (C4H)......................................................................... 135 VgSorcSel: Vg source control (CBH)........................................................................ 137 IDSet: ID setting (CCH) ............................................................................................... 138 NASET: Analog circuit setting (D0H)......................................................................... 139 AutoLoadSet: PROM data auto re-load control (D7H)............................................. 140 EPCTIN: Control PROM WR/RD (E0H) ...................................................................... 141 EPCOUT: PROM control out (E1H) ............................................................................ 142 EPWR: Write to PROM (E2H) ..................................................................................... 143 EPRD: Read from PROM (E3H).................................................................................. 144 PROMSEL: SEL PROM (E4H)..................................................................................... 145 ROMSET: Programmable rom setting (E5H) ............................................................ 146 FRMSEL: Frame Freq. in Temperature range (F0H) ................................................ 147 FRM8SEL: Frame Freq. in Temperature range (idle-8 color) (F1H)........................ 150 TMPRNG: Temp. range set for Frame Freq. Adj. (F2H) ........................................... 152 TMPHYS: Temp. Hysteresis Set for Frame Freq. Adj. (F3H) ................................... 154 TEMPSEL: Temperature Gradient Compensation Coefficient Set (F4H) .............. 156 THYS: Temperature detection threshold (F7H)........................................................ 159
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8.1.63 Frame Set: Frame PWM Set (F9H)............................................................................. 160
9
SPECIFICATIONS.................................................................................162
9.1 9.2 Absolute Maximum Ratings ............................................................................ 162 DC Characteristics.......................................................................................... 163
9.2.1 9.2.2 Basic Characteristics ................................................................................................. 163 Current Consumption (Bare die) ............................................................................... 164
10
10.1 10.2 10.3 10.4
TIMING CHARACTERISTICS.........................................................165
Parallel Interface Characteristics bus (8080-series MCU) .............................. 165 Parallel Interface Characteristics bus (6800-series MCU) .............................. 167 Serial Interface Characteristics (4-pin Serial).................................................. 168 Serial Interface Characteristics (3-pin Serial).................................................. 169
11 12 13
13.1
RESET TIMING...............................................................................170 THE MPU INTERFACE (REFERENCE EXAMPLES) .....................171 APPLICATION NOTE .....................................................................173
Schematic Suggestion .................................................................................... 173
13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.1.6 13.1.7 13.1.8 80-8bit parallel interlace Mode................................................................................... 173 80-16bit parallel interlace Mode................................................................................. 174 68-8bit parallel interlace Mode................................................................................... 175 68-16bit parallel interlace Mode................................................................................. 176 3-line serial interlace Mode ........................................................................................ 177 4-line serial interlace Mode ........................................................................................ 178 80-8bit parallel interlace Mode while typical Vddi=3V/3.3V .................................... 179 4-line serial interlace Mode while typical Vddi=3V/3.3V ......................................... 180
13.2 13.3 13.4 13.5 13.6 13.7 13.8
Power on flow and sequence:......................................................................... 181 Power off flow and sequence.......................................................................... 182 PROM Burning Flow: ...................................................................................... 183 Software coding flow:...................................................................................... 184 Timing sequence of each power level in initial and program flow: .................. 188 Suggestion circuit: .......................................................................................... 189 ESD Protection: .............................................................................................. 190
14
REVISION HISTORY ......................................................................191
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LIST OF FIGURES
Figure 1 Parallel Data Transfer Example Chart ................................................................................................ 31 Figure 2 Write / Read Operation between MPU and ST7687A......................................................................... 36 Figure 3 Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)..................... 39 Figure 4 Rolling Scroll Definition ....................................................................................................................... 41 Figure 5 AC characteristics of Tearing Effect Signal......................................................................................... 45 Figure 6 2-frame AC Driving Waveform (Duty Ratio: 1/128) ............................................................................. 47 Figure 7 N-Line Inversion Driving Waveform (N=10, Duty Ratio=1/128) .......................................................... 47 Figure 8 DC/DC Booster Block Diagram ........................................................................................................... 50 Figure 9 Relationship of V0 and Temperature Compensation........................................................................... 52 Figure 10 V0 value control for different modules by loading PROM offset ....................................................... 54 Figure 11 Relationship of Frequency and Temperature Compensation ............................................................ 55
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LIST OF TABLES
Table 1 Parallel / Serial Interface Mode............................................................................................................. 30 Table 2 Parallel Data Transfer ........................................................................................................................... 30 Table 3 Fixed Constant Value For V0 Setting.................................................................................................... 51
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1 INTRODUCTION
The ST7687A is a driver & controller LSI for 65K color graphic dot-matrix liquid crystal display systems. It generates 384 Segment and 128 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI) or 8-bit/16-bit parallel display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components
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FEATURES
Driver Output Circuits 384 segment outputs / 128 common outputs
Applicable Duty Ratios Various partial display Partial window moving & data scrolling
Gray-Scale Display 4FRC & 31 PWM function circuit to display 64 gray-scale display Support 8 color mode (Idle mode)
On-Chip Display Data RAM Capacity: 128 x 128 x 16 =262,144 bits
Color Support By Interface 4k colors (RGB)=(444) mode 65K colors (RGB)=(565) mode
Microprocessor Interface 8/16-bit parallel bi-directional interface with 6800-series or 8080-series 4-line serial interface 3-line (9-bits) serial interface
On-chip Low Power Analog Circuit On-chip oscillator circuit Voltage converter (x5~x8) with internal capacitors. Extremely Few Outsider Components. On-chip Voltage Regulator On-chip electronic contrast control function Voltage follower (LCD bias: 1/7~1/12)
Operating Voltage Range Supply Digital Voltage VDDI(VDD): 1.65 to 3.3V Supply Analog Voltage VDDA(VDD2, VDD3, VDD4, VDD5): 2.4 to 3.3V LCD driving voltage (VOP = V0 - VSS): Max: 18V
LCD Driving Voltage Contrast Adjustment Value is stored in the Built-In PROM (Programable ROM) for better display quality. LCD Driving Setting Suggestion VOP = 14V, BIAS=1/9. (VDD=2.8V)
Package Type Application for COG
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3 PAD ARRANGEMENT (COG)
Chip Size :
11586 um x 686 um
Bump Pitch :
149 COM27
......
135 VSS 134 Vgin 127 Vgin 126 Vgs 125 Vgout 124 Vgout 123 XV0in 122 XV0in 121 XV0in 120 XV0in 119 XV0s 118 XV0out 117 XV0out 116 V0out 115 V0out 114 V0s 113 V0in 112 V0in 111 V0in 110 V0in 109 Vm 104 Vm 103 VSS2
PAD 136~148, 149~212, 213~596, 597~660 661~673 pitch=22um (min, com/seg) PAD 212~213, 596~597 pitch=110.88um ( com/seg) PAD 1~7, 10~13, 32~38, 41~57, 59~135 pitch=80um (I/O) PAD 14~29, pitch=120um(I/O) PAD 8~9, 30~31, 39~40, pitch=49um(I/O) PAD 7~8, 9~10, 31~32, 38~39, 40~41, pitch=64.5um(I/O) PAD 57~58, 58~59=75.5um(I/O) PAD 13~14, pitch=100um(I/O) PAD 29~30, pitch=84.5um(I/O)
199 COM127 200 DUMMY 212 DUMMY 213 SEG0
94 VSS2 93 VDD2 86 VDD2 85 VDD5 80 VDD5 79 VDD4 78 VDD4 77 VDD3 76 VDD3 75 VREF 74 VSS4 73 VSS4 72 VSS4 71 VSS2
Bump Size :
PAD 136~673 Bump width=10.5um (min, com/seg) Bump space=11.5um (min, com/seg) Bump length=166.7um(min, com/seg) Bump area=1750.35um^2(com/seg) PAD 58 Bump width=56um(I/O) Bump space=15um(I/O) Bump length=59um(I/O) Bump area=3304um^2 PAD 1~7, 10~13, 32~38, 41~57, 59~135 Bump width=65um(I/O) Bump space=15um(I/O) Bump length=59um(I/O) Bump area=3185um^2 PAD 14~29 Bump width=105um(I/O) Bump space=15um(I/O) Bump length=59um(I/O) Bump area=6195um^2 PAD 8~9, 30~31, 39~40 Bump width=34um(I/O) Bump space=15um(I/O) Bump length=59um(I/O) Bump area=2006um^2
62 VSS2 61 VSS 60 VSS 59 VSS 58 VSS 57 VSS 56 VSS1 55 VSS1
X
54 VD1out 53 VD1out 52 VD1in 51 VD1in 50 VD1in 49 VD1in 48 VDD 47 VDD 46 VDD 45 VDD 44 TCAP 43 TE 42 /EXT 41 /CS 40 VDD 39 VSS 38 IF3 37 IF2 36 IF1 35 /RST 34 A0 33 RW_WR 32 E_RD 31 VDD 30 VSS 29 D15 28 D14 27 D13 26 D12 25 D11 24 D10 23 D9 22 D8 21 D7 20 D6 19 D5 18 D4 17 D3 16 D2
Y
(0,0)
ST7687A-G4 (Bump Height: 15 um, Hardness: 55HV) ST7687A-G4-1 (Bump Height: 12 um, Hardness: 90HV) Chip Thickness: 300 um Alignment mark The center of alignment mark: see bellow Table
596 SEG383 597 DUMMY 609 DUMMY 610 COM126
15 D1 14 D0 13 RW_WR 12 VDD 11 A0 10 INTVD1 9 VDD 8 VSS 7 CLS 6 CL 5 VPP 4 VPP 3 VPP 2 VPP 1 VSS
......
660 COM26
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PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
PAD CENTER COORDINATES
NAME VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST X -5582.5 -5502.5 -5422.5 -5342.5 -5262.5 -5182.5 -5102.5 -5038 -4989 -4924.5 -4844.5 -4764.5 -4684.5 -4584.5 -4464.5 -4344.5 -4224.5 -4104.5 -3984.5 -3864.5 -3744.5 -3624.5 -3504.5 -3384.5 -3264.5 -3144.5 -3024.5 -2904.5 -2784.5 -2700 -2651 -2586.5 -2506.5 -2426.5 -2346.5 Y -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 PAD 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 NAME IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 X -2266.5 -2186.5 -2106.5 -2042 -1993 -1928.5 -1848.5 -1768.5 -1688.5 -1608.5 -1528.5 -1448.5 -1368.5 -1288.5 -1208.5 -1128.5 -1048.5 -968.5 -888.5 -808.5 -728.5 -648.5 -573 -497.5 -417.5 -337.5 -257.5 -177.5 -97.5 -17.5 62.5 142.5 222.5 302.5 382.5 Y -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5
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PAD 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 NAME VSS2 VSS4 VSS4 VSS4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 Vm Vm Vm X 462.5 542.5 622.5 702.5 782.5 862.5 942.5 1022.5 1102.5 1182.5 1262.5 1342.5 1422.5 1502.5 1582.5 1662.5 1742.5 1822.5 1902.5 1982.5 2062.5 2142.5 2222.5 2302.5 2382.5 2462.5 2542.5 2622.5 2702.5 2782.5 2862.5 2942.5 3022.5 3102.5 3182.5 3262.5 Y -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 PAD 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 NAME Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS COM1 COM3 COM5 COM7 COM9 COM11 COM13 X 3342.5 3422.5 3502.5 3582.5 3662.5 3742.5 3822.5 3902.5 3982.5 4062.5 4142.5 4222.5 4302.5 4382.5 4462.5 4542.5 4622.5 4702.5 4782.5 4862.5 4942.5 5022.5 5102.5 5182.5 5262.5 5342.5 5422.5 5502.5 5582.5 5642.23 5642.23 5642.23 5642.23 5642.23 5642.23 5642.23 Y -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -257.5 -189.26 -167.26 -145.26 -123.26 -101.26 -79.26 -57.26
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PAD 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 NAME COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 COM65 COM67 COM69 COM71 COM73 COM75 COM77 COM79 COM81 COM83 COM85 X 5642.23 5642.23 5642.23 5642.23 5642.23 5642.23 5709.88 5687.88 5665.88 5643.88 5621.88 5599.88 5577.88 5555.88 5533.88 5511.88 5489.88 5467.88 5445.88 5423.88 5401.88 5379.88 5357.88 5335.88 5313.88 5291.88 5269.88 5247.88 5225.88 5203.88 5181.88 5159.88 5137.88 5115.88 5093.88 5071.88 Y -35.26 -13.26 8.74 30.74 52.74 74.74 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 PAD 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 NAME COM87 COM89 COM91 COM93 COM95 COM97 COM99 COM101 COM103 COM105 COM107 COM109 COM111 COM113 COM115 COM117 COM119 COM121 COM123 COM125 COM127 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG0 SEG1 X 5049.88 5027.88 5005.88 4983.88 4961.88 4939.88 4917.88 4895.88 4873.88 4851.88 4829.88 4807.88 4785.88 4763.88 4741.88 4719.88 4697.88 4675.88 4653.88 4631.88 4609.88 4587.88 4565.88 4543.88 4521.88 4499.88 4477.88 4455.88 4433.88 4411.88 4389.88 4367.88 4345.88 4323.88 4213 4191 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83
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PAD 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 NAME SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 X 4169 4147 4125 4103 4081 4059 4037 4015 3993 3971 3949 3927 3905 3883 3861 3839 3817 3795 3773 3751 3729 3707 3685 3663 3641 3619 3597 3575 3553 3531 3509 3487 3465 3443 3421 3399 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 PAD 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 NAME SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 X 3377 3355 3333 3311 3289 3267 3245 3223 3201 3179 3157 3135 3113 3091 3069 3047 3025 3003 2981 2959 2937 2915 2893 2871 2849 2827 2805 2783 2761 2739 2717 2695 2673 2651 2629 2607 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83
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PAD 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 NAME SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 X 2585 2563 2541 2519 2497 2475 2453 2431 2409 2387 2365 2343 2321 2299 2277 2255 2233 2211 2189 2167 2145 2123 2101 2079 2057 2035 2013 1991 1969 1947 1925 1903 1881 1859 1837 1815 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 PAD 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 NAME SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 X 1793 1771 1749 1727 1705 1683 1661 1639 1617 1595 1573 1551 1529 1507 1485 1463 1441 1419 1397 1375 1353 1331 1309 1287 1265 1243 1221 1199 1177 1155 1133 1111 1089 1067 1045 1023 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83
Ver. 1.0
15/191
2009/12
ST7687A
PAD 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 NAME SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 SEG166 SEG167 SEG168 SEG169 SEG170 SEG171 SEG172 SEG173 SEG174 SEG175 SEG176 SEG177 SEG178 SEG179 SEG180 SEG181 X 1001 979 957 935 913 891 869 847 825 803 781 759 737 715 693 671 649 627 605 583 561 539 517 495 473 451 429 407 385 363 341 319 297 275 253 231 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 PAD 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 NAME SEG182 SEG183 SEG184 SEG185 SEG186 SEG187 SEG188 SEG189 SEG190 SEG191 SEG192 SEG193 SEG194 SEG195 SEG196 SEG197 SEG198 SEG199 SEG200 SEG201 SEG202 SEG203 SEG204 SEG205 SEG206 SEG207 SEG208 SEG209 SEG210 SEG211 SEG212 SEG213 SEG214 SEG215 SEG216 SEG217 X 209 187 165 143 121 99 77 55 33 11 -11 -33 -55 -77 -99 -121 -143 -165 -187 -209 -231 -253 -275 -297 -319 -341 -363 -385 -407 -429 -451 -473 -495 -517 -539 -561 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83
Ver. 1.0
16/191
2009/12
ST7687A
PAD 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 NAME SEG218 SEG219 SEG220 SEG221 SEG222 SEG223 SEG224 SEG225 SEG226 SEG227 SEG228 SEG229 SEG230 SEG231 SEG232 SEG233 SEG234 SEG235 SEG236 SEG237 SEG238 SEG239 SEG240 SEG241 SEG242 SEG243 SEG244 SEG245 SEG246 SEG247 SEG248 SEG249 SEG250 SEG251 SEG252 SEG253 X -583 -605 -627 -649 -671 -693 -715 -737 -759 -781 -803 -825 -847 -869 -891 -913 -935 -957 -979 -1001 -1023 -1045 -1067 -1089 -1111 -1133 -1155 -1177 -1199 -1221 -1243 -1265 -1287 -1309 -1331 -1353 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 PAD 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 NAME SEG254 SEG255 SEG256 SEG257 SEG258 SEG259 SEG260 SEG261 SEG262 SEG263 SEG264 SEG265 SEG266 SEG267 SEG268 SEG269 SEG270 SEG271 SEG272 SEG273 SEG274 SEG275 SEG276 SEG277 SEG278 SEG279 SEG280 SEG281 SEG282 SEG283 SEG284 SEG285 SEG286 SEG287 SEG288 SEG289 X -1375 -1397 -1419 -1441 -1463 -1485 -1507 -1529 -1551 -1573 -1595 -1617 -1639 -1661 -1683 -1705 -1727 -1749 -1771 -1793 -1815 -1837 -1859 -1881 -1903 -1925 -1947 -1969 -1991 -2013 -2035 -2057 -2079 -2101 -2123 -2145 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83
Ver. 1.0
17/191
2009/12
ST7687A
PAD 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 NAME SEG290 SEG291 SEG292 SEG293 SEG294 SEG295 SEG296 SEG297 SEG298 SEG299 SEG300 SEG301 SEG302 SEG303 SEG304 SEG305 SEG306 SEG307 SEG308 SEG309 SEG310 SEG311 SEG312 SEG313 SEG314 SEG315 SEG316 SEG317 SEG318 SEG319 SEG320 SEG321 SEG322 SEG323 SEG324 SEG325 X -2167 -2189 -2211 -2233 -2255 -2277 -2299 -2321 -2343 -2365 -2387 -2409 -2431 -2453 -2475 -2497 -2519 -2541 -2563 -2585 -2607 -2629 -2651 -2673 -2695 -2717 -2739 -2761 -2783 -2805 -2827 -2849 -2871 -2893 -2915 -2937 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 PAD 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 NAME SEG326 SEG327 SEG328 SEG329 SEG330 SEG331 SEG332 SEG333 SEG334 SEG335 SEG336 SEG337 SEG338 SEG339 SEG340 SEG341 SEG342 SEG343 SEG344 SEG345 SEG346 SEG347 SEG348 SEG349 SEG350 SEG351 SEG352 SEG353 SEG354 SEG355 SEG356 SEG357 SEG358 SEG359 SEG360 SEG361 X -2959 -2981 -3003 -3025 -3047 -3069 -3091 -3113 -3135 -3157 -3179 -3201 -3223 -3245 -3267 -3289 -3311 -3333 -3355 -3377 -3399 -3421 -3443 -3465 -3487 -3509 -3531 -3553 -3575 -3597 -3619 -3641 -3663 -3685 -3707 -3729 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83
Ver. 1.0
18/191
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ST7687A
PAD 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 NAME SEG362 SEG363 SEG364 SEG365 SEG366 SEG367 SEG368 SEG369 SEG370 SEG371 SEG372 SEG373 SEG374 SEG375 SEG376 SEG377 SEG378 SEG379 SEG380 SEG381 SEG382 SEG383 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM126 X -3751 -3773 -3795 -3817 -3839 -3861 -3883 -3905 -3927 -3949 -3971 -3993 -4015 -4037 -4059 -4081 -4103 -4125 -4147 -4169 -4191 -4213 -4323.88 -4345.88 -4367.88 -4389.88 -4411.88 -4433.88 -4455.88 -4477.88 -4499.88 -4521.88 -4543.88 -4565.88 -4587.88 -4609.88 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 PAD 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 NAME COM124 COM122 COM120 COM118 COM116 COM114 COM112 COM110 COM108 COM106 COM104 COM102 COM100 COM98 COM96 COM94 COM92 COM90 COM88 COM86 COM84 COM82 COM80 COM78 COM76 COM74 COM72 COM70 COM68 COM66 COM64 COM62 COM60 COM58 COM56 COM54 X -4631.88 -4653.88 -4675.88 -4697.88 -4719.88 -4741.88 -4763.88 -4785.88 -4807.88 -4829.88 -4851.88 -4873.88 -4895.88 -4917.88 -4939.88 -4961.88 -4983.88 -5005.88 -5027.88 -5049.88 -5071.88 -5093.88 -5115.88 -5137.88 -5159.88 -5181.88 -5203.88 -5225.88 -5247.88 -5269.88 -5291.88 -5313.88 -5335.88 -5357.88 -5379.88 -5401.88 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83
Ver. 1.0
19/191
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ST7687A
PAD 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 NAME COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10 COM8 COM6 COM4 COM2 COM0 LMARK1 LMARK2 X -5423.88 -5445.88 -5467.88 -5489.88 -5511.88 -5533.88 -5555.88 -5577.88 -5599.88 -5621.88 -5643.88 -5665.88 -5687.88 -5709.88 -5642.23 -5642.23 -5642.23 -5642.23 -5642.23 -5642.23 -5642.23 -5642.23 Y 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 203.83 74.74 52.74 30.74 8.74 -13.26 -35.26 -57.26 -79.26
-5642.23 -101.26 -5642.23 -123.26 -5642.23 -145.26 -5642.23 -167.26 -5642.23 -189.26 -5717.5 5717.5 -267.5 -267.5
Ver. 1.0
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ST7687A
TCAP
D0 to D15
TE
E_RD
A0 /CS /RST
/EXT
BLOCK DIAGRAM
INTVD1
IF3 IF2 IF1
5
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RW_WR
2009/12
ST7687A
6
6.1
Name VDD VDD2 VDD3 VDD4 VDD5 VSS VSS1 VSS2 VSS4
PIN DESCRIPTION
Power Supply
I/O Supply Supply Supply Supply Supply Supply Supply Supply Supply Power supply for logic circuit. Power supply for Booster circuit. Power supply for LCD. Power supply for LCD. Power supply for LCD. Ground for logic circuit. Ground system should be connected together. Ground for OSC circuit. Ground system should be connected together. Ground for Booster circuit. Ground system should be connected together. Ground for LCD. Ground system should be connected together. Description
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ST7687A
6.2
Name
LCD Power Supply Pins
I/O Positive LCD driver supply voltages. Description
V0OUT V0IN V0S I/O
V0OUT is the output voltage of V0 generated by ST7687A. V0IN is the input pin of power supply to generate V0 voltage for LCD. V0S is the input pin of power supply to sense the V0 voltage. V0OUT V0IN & V0S should be connected together by FPC. Negative LCD driver supply voltages.
XV0OUT XV0IN XV0S I/O
XV0OUT is the output voltage of XV0 generated by ST7687A. XV0IN is the input pin of power supply to generate XV0 voltage for LCD. XV0S is the input pin of power supply to sense the XV0 voltage. XV0OUT XV0IN & XV0S should be connected together by FPC. Bias LCD driver supply voltages. VgOUT is the output voltage of Vg generated by ST7687A. VgIN is the input pin of power supply to generate Vg voltage for LCD. VgS is the input pin of power supply to sense the Vg voltage. VgOUT VgIN & VgS should be connected together by FPC.
VgOUT VgIN VgS Vm I/O
Vm is the I/O pin of LCD bias supply voltage. Voltages should have the following relationship; V0 Vg Vm VSS XV0. VDDA-0.7VVm0.9V , 2 x VDDA-0.6VVg1.8V When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias
NOTE: N = 7 to 12
Vg (2/N) x V0
Vm (1/N) x V0
Voltage regulator for digital circuit. VD1out VD1in VD1out is voltage output from regulator circuit. I/O VD1in is voltage input to digital circuit. VD1in and VD1out should be connected together by FPC.
Note: Refer to INTVD1 description
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ST7687A
6.3
Name CLS CL VREF TCAP VPP
System Control
I/O I I/O O I/O I Reserved for testing only. Please fix this pin to VDD. Reserved for testing only. Leave this pin open. Reference voltage output for monitor only. Left it opened. Test pin. Left it opens. When writing PROM, it needs outer power supply voltage 6.5~6.75V (>8mA) input to write successfully. Typical VDDI 1.8V Tolerance Level of INTVD1 Capacitor of VD1 to VSS 1.65V~2.9V VSS VSS 2.9V~3.3V VDD VDD Unnecessary Unnecessary necessary necessary Description
INTVD1
I
2.8V 3.0V 3.3V
Ver. 1.0
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ST7687A
6.4
Name /RST
Microprocessor Interface
I/O I Reset input pin When /RST is "L", initialization is executed. Parallel / Serial data input select input IF3 H H IF2 H H L L H H IF1 H L H L H L MPU interface type 80 series 16-bit parallel 80 series 8-bit parallel 68 series 16-bit parallel 68 series 8-bit parallel 8-bit serial (4 line) 9-bit serial (3 line) Description
IF[3:1]
I
H H L L
Note:
Refer to Table 1 for detail interface connections.
Chip select input pins /CS I Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D15 become high impedance. Register select input pin In parallel interface: A0 I A0 = "H": D0 to D15 or SI are display data A0 = "L": D0 to D15 or SI are control Command In 3-line/4-line interface: This pad will be used for SCL function. RW_WR pin is only used in parallel interface. MPU type RW_WR Description Read / Write control input pin 6800-series RW_WR I RW Write status: RW = "L". Read status: RW = "H". Write enable clock input pin 8080-series /WR The data on D0 to D15 are latched at the rising edge of the /WR signal. When in the serial interface, connect it to VDDI.
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ST7687A
E_RD pin is only used in parallel interface. MPU Type E_RD Description Enable clock pin: Write status: The data on D0 to D15 are 6800-series E_RD I E latched at the falling edge of the E signal. Read status: The data on D0 to D15 are latched at the rising edge of the E signal. Read enable clock input pin 8080-series /RD The data on D0 to D15 are latched at the falling edge of the /WR signal. When in the serial interface, connect it to VDDI. They connect to the standard 8/16-bit MPU bus via the 8/16bit bi-directional bus. When the following interface is selected and the /CS pin is high, the following pins become high impedance. 1. In 8-bit parallel: D15-D8 pins are in the state of high impedance should connect to D15 to D0 I/O VDDI 2. In 3-line/4-line interface D0 pad will be used for SI function 3. In 4-line interface D1 pad will be used for A0 function 4. In Serial interface: unused pins are in the state of high impedance should connect to VDDI. SI I SI is used to input serial data when the serial interface is selected.(3 line and 4 line) It is used by "D0" pad, See Table 1. SCL is used to input serial clock when the serial interface is selected. SCL I The data is converted in the rising edge. (3 line and 4 line) It is used by "A0" pad, See Table 1. TE O Tearing effect output. PROM burn-in control Pin. /EXT I There is a pull-high resistor between /EXT &VDD in ST7687A. When burning PROM, please add an external VSS on /EXT. (needs external power supply voltage VPP=6.5V)
NOTE: 1. Microprocessor interface pins should not be floating in any operation mode. Unused pin should connect to VDDI (Supply Digital Voltage).
2.
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ST7687A
6.5
Name
LCD Driver Outputs
I/O LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data M (Internal) H L H L Sleep-In mode Segment driver output voltage Normal display Reverse display VSS Vg Vg VSS VSS Description
SEG0 to SEG383 O
H H L L
Vg VSS VSS Vg VSS
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data COM0 to COM127 O H H L L Sleep-In mode M (Internal) H L H L Common driver output voltage XV0 V0 Vm Vm VSS
DUMMY
-
It's reserved for test, do not connect ITO or any other electrical-conducted material with it.
Ver. 1.0
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ST7687A
Driving Waveform
ST7687A I/O PIN ITO Resister Limitation Pin Name VDD, VDD2~VDD5, VSS,VSS1,VSS2,VSS4,SI(in parallel interface is D0), VD1in, VD1out V0IN, V0OUT, V0S ,XV0IN, XV0OUT ,XV0S , VgIN, VgOUT ,VgS ,Vm VPP A0, E_RD, RW_WR, /CS, D0(in parellel interface),D1, ...D15, (SCL), TE, INTVD1 /RST IF[3:1], CLS, /EXT TCAP, CL, VREF
NOTE: 1. Make sure that the ITO resistance of COM0 ~ COM127 is equal, and so is it of SEG0 ~ SEG383. These limitations include the bottleneck of ITO layout. 2. ITO layout suggestion is shown as below:
ITO Resister <100 <300 <50 <1K <10K <1K Floating
Ver. 1.0
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ST7687A
7
7.1
FUNCTIONAL DESCRIPTION
Microprocessor Interface
Chip Select Input /CS pin is chip selection. The ST7687A is active when /CS=L. In serial interface mode, the internal shift
register and the counter are reset when /CS=H.
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ST7687A
7.2 Selecting Parallel / Serial Interface
ST7687A has four types of interfaces with an MPU, which are two serial and two parallel interfaces. These parallel or serial interfaces are determined by IF pin as shown in Table 1. I/F Mode IF3 H H H H L L IF2 H H L L H H IF 1 H L H L H L 80 serial 16-bit parallel 80 serial 8-bit parallel 68 serial 16-bit parallel 68 serial 8-bit parallel 8-bit SPI mode (4 line) 9-bit SPI mode (3 line) I/F Description /CS /CS /CS /CS /CS /CS /CS A0 A0 A0 A0 A0 SCL SCL E_RD /RD /RD E E --RW_WR /WR /WR R/W R/W --Used Data Bus D15~D2 D7~D2 D15~D2 D7~D2 --D1 D1 D1 D1 D1 A0 -D0 D0 D0 D0 D0 SI SI Pin Assignment
Table 1 Parallel / Serial Interface Mode
7.2.1
8-bit or 16-bit Parallel Interface
The ST7687A identifies the type of the data bus signals according to the combination of A0, /RD (E) and /WR (R/W) signals, as shown in Table 2. Common A0 H H L H 6800-series R/W H H L L E 8080-series /WR H H /RD H H Display data read out Register status read Instruction write Display data write
Description
Table 2 Parallel Data Transfer
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ST7687A
Figure 1 Parallel Data Transfer Example Chart
Relation between Data Bus and Gradation Data ST7687A offers 4096, 65K color display. When using 4096, 65K color display; you can specify color for each of R, G, and B using the palette function. Use the command for switching between these modes. (1) 4096-color display (1-1) Type A 4096 color display 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGG D7, D6, D5, D4, D3, D2, D1, D0: BBBBRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB There are 3 write operations for 2 pixel data. 1st pixel data is written in the display data RAM when 2nd -write operation finishes, and 2nd pixel data is written in the display data RAM when 3rd-write operation finishes. 2. 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGGBBBBXXXX 1st-write There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. "X" are ignored dummy bits. (1-2) Type B 4096 color display 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB There are 2 write operations for 1 pixel data. 1st pixel data is written in the display data RAM when 2nd -write operation finishes. "X" are ignored dummy 1st-write 2nd-write 1st-write 2nd-write 3rd-write
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ST7687A
bits. 2. 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRRGGGGBBBB 1st-write There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. "X" are ignored dummy bits. (2) 65K color input mode 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGG D7, D6, D5, D4, D3, D2, D1, D0: GGGBBBBB There are 2 write operations for 1 pixel data. 1st pixel data is written in the display data RAM when 2nd -write operation finishes. 2. 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGGGGGBBBBB 1st-write There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. 7.2.2 8- and 9-bit Serial Interface 1st-write 2nd-write
The 8-bit serial interface uses four pins /CS, SI, SCL, and A0 to write in commands and data. Meanwhile, the 9-bit serial interface uses three pins /CS, SI and SCL for the same purpose. Data read is not available in the serial interface. Data must write to IC with 8 bits for each time. The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradation. (1) 8-bit serial interface (4-line) When entering data (parameters): A0= HIGH at the rising edge of the 8 SCL.
th
When entering command: A0= LOW at the rising edge of the 8 SCL
th
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ST7687A
When entering reading command:
(2) 9-bit serial interface (3-line) When entering data (parameters): SI= HIGH at the rising edge of the 1 SCL.
st
When entering command: SI= LOW at the rising edge of the 1 SCL.
st
When entering reading command:
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ST7687A
If /CS is set to HIGH while the 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering succeeding sets of data, you must correctly input the data concerned again. In order to avoid data transfer error due to incoming noise, it is recommended to set /CS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register.
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ST7687A
7.2.3 8-bit and 9-bit Serial Interface Data Color Coding (1) 8-bit serial interface (4-line) R 5-bit, G 6-bit, B 5-bit, 65,536 colors There is 1 pixel ( = 3 sub-pixels ) per 2 byte.
(2) 9-bit serial interface (3-line) R 5-bit, G 6-bit, B 5-bit, 65,536 colors There is 1 pixel ( = 3 sub-pixels ) per 2 byte.
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7.3 Access to DDRAM and Internal Registers
ST7687A realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. Figure 2 illustrates these relations. In 80-series interface mode:
MPU signal
Read Operation
A0 /WR /RD DATA Internal signals /WR /RD N Dummy D (N ) D (N +1)
INTERNAL LATCH ADDRESS COUNTER
N D (N )
D (N ) D (N +1)
D (N +1) D (N +2)
D (N +2) D (N +3)
Figure 2 Write / Read Operation between MPU and ST7687A
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7.4
7.4.1
Display Data RAM (DDRAM)
DDRAM
It is 128 X 128 X 16 bits capacity RAM prepared for storing dot data. Refer to the following memory map for the RAM configuration.
Memory Map
RGB alignment Data control command
(MADCTR) MX=0 (MADCTR) MX=1 Color Data Page (MADCTR)
MY=0
Column 0 127 R G B R 1 126 G B R 127 0 G B
(MADCTR)
MY=1
0 1 2 3 4 5 6 7 : 120 121 122 123 124 125 126 127 SEGout
127 126 125 124 123 122 121 120 : 7 6 5 4 3 2 1 0 0 1 2 3 4 5 381 382 383
You can change position of R and B with MADCTR command.
7.4.2
Address Control
The address counter sets the addresses of the display data RAM for writing. Data is written pixel into the RAM matrix of ST7687A. The data for one pixel or two pixels is collected (RGB 5-6-5-bit), according to the data formats. As soon as this pixel-data information is complete, the "Write access" is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=127 (7Fh) and Y=0 to Y=127 (7Fh). Addresses outside these ranges are not allowed.
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Before writing to the RAM, a window must be defined into which will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=127 (7Fh), YE=127 (7Fh). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (MV=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands "CASET, RASET" and "MADCTR", define flags MV, MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Figure 3 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data must be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as below: Condition When RAMWR command is accepted Column Counter Return to "Start Column (XS)" Complete Pixel Read / Write action Increment by 1 Row Counter Return to "Start Row (YS)" No change
The Column counter value is larger than "End Column (XE)"
Return to "Start Column (XS)"
Increment by 1
The Column counter value is larger than "End Column (XE)" and the Row counter value is larger than "End Row (YE)"
Return to "Start Column (XS)"
Return to "Start Row (YS)"
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Display Data Direction MADCTR Parameter MV MX MY Image in the Host (MPU) Image in the Driver (DDRAM)
Normal
0
0
0
Y-Mirror
0
0
1
X-Mirror
0
1
0
X-Mirror Y-Mirror
0
1
1
X-Y Exchange
1
0
0
X-Y Exchange Y-Mirror X-Y Exchange X-Mirror X-Y Exchange X-Mirror Y-Mirror
Figure 3 Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)
1
0
1
1
1
0
1
1
1
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7.4.3 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU's read or write of DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM when the LCD is turned on does not cause troubles such as flicking of the display images. 7.4.4 Scroll Address Circuit
The circuit associates lines on DDRAM with COM output. ST7687A processes signals for the liquid crystal display on 1-line basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in line. 7.4.5 Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM. 7.4.6 Normal Display On or Partial Mode On, Vertical Scroll Off
In this mode, contents of the frame memory within an area where column address is 00h to 7Fh and row address is 00h to 7Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column address, row address) = (0, 0). Example1) Normal Display On
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Example2) Partial Display On: PSL[6:0] = 04h, PEL[6:0] = 7Ch, MADCTR (ML)=0
7.4.7
7.4.7.1
Vertical Scroll/Rolling Scroll
Rolling Scroll
There is just one types of vertical scrolling, which are determined by the commands "Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h).
Figure 4 Rolling Scroll Definition
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =128. In this case, `rolling' scrolling is applied as shown below. All the memory contents will be used. Example1) Panel size=128 x 128, TFA =3, VSA=123, BFA=2, SSA=4, MADCTR ML=0: Rolling Scroll
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Example2) Panel size=128 x 128, TFA =3, VSA=123, BFA=2, SSA=4, MADCTR ML=1: Rolling Scroll (TFA and BFA are exchanged)
7.4.7.2
Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands "Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h). Case 1: TFA + VSA + BFA<128 N/A. Do not set TFA + VSA + BFA<128. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=128 (Rolling Scrolling) Example1) When MADCTR parameter ML="0", TFA=0, VSA=128, BFA=0 and VSCSAD=40.
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Example2) When MADCTR parameter ML="1", TFA=10, VSA=118, BFA=0 and VSCSAD=30.
2 1 1 2 2 1 2 3 2 1 3 1 1 2 3 1 2 3 1 2
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7.4.8 Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.
7.4.8.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Sync (tVHD) information. It starts at 111th line signal and ends at the 128th line signal. There is one high pulse during each frame. Mode 2, the Tearing Effect Output signal consists of both H-Sync (tHDH) and V-Sync (tVDH) information. TE pin outputs tHDH pulse on each COM scan signal. During 111th ~ 128th line signal, it output a high pulse which equals: 1 tHDH + 1 tVDH.
Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low.
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7.4.8.2 Tearing Effect Line Timing
The Tearing Effect signal is described below:
Figure 5 AC characteristics of Tearing Effect Signal
Idle Mode Off (Frame Rate = 77Hz, Nline=0x00)
Symbol tVDL tVDH tHDL tHDH
Parameter Vertical Timing Low Duration Vertical Timing High Duration Horizontal Timing Low Duration Horizontal Timing High Duration
Min -1 3
Typ 11.11 1.82 92 6
Max -----
Unit ms ms us us
Description Mode1
Mode2
Note: The signal's rise and fall time (tf, tr) are stipulated to be equal to or less than 15ns.
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7.5 Gray-Scale Display
ST7687A incorporates a 4FRC & 31 PWM function circuit to display a 64 gray-scale display.
7.6
Oscillation circuit
ST7687A is built-in an oscillator circuit. It provides internal clock without external resistor. This oscillator
signal is used in the voltage converter and display timing generation circuit.
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7.7 Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, which is generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 128-pixels display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M), which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 6.
Figure 6 2-frame AC Driving Waveform (Duty Ratio: 1/128)
126 127 0 1 2 3 4 5 6 7 89 10 11 119 127 125 121 123 126 0 120 122 124 1 2 34
Fosc FR(Internal) M(Internal)
COM0
COM10
SEGn
Figure 7 N-Line Inversion Driving Waveform (N=10, Duty Ratio=1/128)
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7.8
7.8.1
POWER LEVEL DEFINITION
Power ON/OFF SEQUENCE
NOTE: VDDI=VDD; VDDA=VDD2, VDD3, VDD4, VDD5
During power off, if LCD is in the Sleep Out mode, VDDA and VDDI must be powered down minimum 120msec after /RST has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDDA can be powered down minimum 0msec after /RST has been released. /CS can be applied at any timing or can be permanently grounded. /RST has priority over /CS. If /RST line is not held stable by host during Power On Sequence as defined in Sections case1 and case2, then it will be necessary to apply a Hardware Reset (/RST) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below: /RST line is held High or Unstable by Host at Power On If /RST line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDDA and VDDI have been applied - otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
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7.8.2 Power Levels 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out: In this mode, the display is able to show maximum 65K colors. 2. Partial Mode On, Idle Mode Off, Sleep Out: In this mode part of the display is used with maximum 65K colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out: In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out: In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode: In this mode, the DC:DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with Digital VDD power supply. Contents of the memory are safe. 6. Power Off Mode: In this mode, both Analog VDD and Digital VDDI are removed.
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
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7.9 Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Figure 8 shows the referenced combinations in using Power Supply circuits.
IC Internal Booster 1 ( x8 ) V0
IC External
Booster 2 ( x2 ) VDD2 VSS2
Vg
1.0uF/25V Non-Polar
VSS2
1.0uF/16V Non-Polar
Booster 3 ( -x8 )
XV0
Figure 8 DC/DC Booster Block Diagram
7.9.1
Voltage Regulator Circuits
There is a built-in voltage regulator circuits in ST7687A for generating V0. After internal voltage is regulated by voltage regulator circuit, V0 is generated. Detail explanation of V0 set is listed below:
7.9.1.1 Set V0 (Temperatue = 24)
V0=a+{Vop[8:0]+Vop-offset[6:0]+(EV[6:0]-3Fh)}xb (V)
Example: Vop[8:0]=011010010 Vop-offset[6:0]=0000000 EV[6:0]=0111111 V0=3.6 + { 210 + 0 + (63-63) } x 0.04 =12 (V)
a is a fixed constant value (see Table 3). b is a fixed constant value (see Table 3). Vop [8:0] is the programmed VOP value. The programming range for Vop [8:0] is 0 to 410 (19Ahex). The range of contrast is 128 steps for fine tuning VOP.
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SYMBOL a b VALUE 3.60 0.04
Table 3 Fixed Constant For V0 Setting
UNIT V V
V0 restriction: Because Vg should larger than 1.8V, ST7687A V0 value should be higher than 1.8 x Bias / 2 (V) and lower than 18V. V0 value outside the available range is undefined. Users has to ensure while selecting the temperature compensation that under all conditions and including all tolerances that the V0 voltage remains in the range.
Bias 1/7 1/8 1/9 1/10 1/11 1/12
Min 6.3 7.2 8.1 9 9.9 10.8
Max 18.00 18.00 18.00 18.00 18.00 18.00
inhibit V0 Range Available V0 Range
1/12
1/11
1/10
Bias
1/9 1/8 1/7
0
2
4
6
8
10
12
14
16
18
20
V0(Voltage)
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7.9.1.2 Set V0 With Temperature Compensation
There are 16-line slope in each temperature steps and customer can select one line slope of temperature compensation coefficiency for each temperature step. Each temperature step is 8 C. Please see Figure 9 as below.
o
Figure 9 Relationship of V0 and Temperature Compensation
In command TEMPSEL (see section 8.1.62) each MTx, where x=0, 1, 2,..., E, F, has a value between 0 and 15. MTx = 0 results in 0V increment on V0, MTx = 1 results in Mx=5mV increment, ..., MTx = 15 results in Mx=15x5mV=75mV increment. Note that each MTx individually corresponds to a temperature interval; The relations between Mx and V0 quantity due to temperature V0(T) are described in the equations shown as follows: Temperature range -40 T -32 -32 T -24 -24 T -16 -16 T -8 -8 T 0 0 T 8 8 T 16 16 T 24 24 T 32 32 T 40 40 T 48 48 T 56 56 T 64 Equation V0(V) at temperature=T V0(T) = V0(T24)+ (-32-T)M0 +( M1 + M2 + M3 + M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (-24-T)M1 +( M2 + M3 + M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (-16-T)M2 +( M3 + M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (-8-T)M3 +( M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (0-T)M4 +( M5 + M6 + M7)8 V0(T) = V0(T24)+ (8-T)M5 +( M6 + M7)8 V0(T) = V0(T24)+ (16-T)M6 + M78 V0(T) = V0(T24)+ (24-T)M7 V0(T) = V0(T24)(T-24)M8 V0(T) = V0(T24)(T-32)M9M88 V0(T) = V0(T24)(T-40)M10(M9 + M8 )8 V0(T) = V0(T24)(T-48)M11(M10 + M9 + M8 )8 V0(T) = V0(T24)(T-56)M12(M11 + M10 + M9 + M8 )8
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64 T 72 72 T 80 80 T 88 V0(T) = V0(T24)(T-64)M13(M12 + M11 + M10 + M9 + M8 )8 V0(T) = V0(T24)(T-72)M14(M13 + M12 + M11 + M10 + M9 + M8 )8 V0(T) = V0(T24)(T-80)M15( M14 + M13 + M12 + M11 + M10 + M9 + M8 )8
Note: Please make sure to avoid any kind of heating source closing to ST7687A such as back light, to prevent Vop is not anticipatve because of temperature compensate circuit worked.
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7.9.1.3 V0 fine tuning
ST7687A has 2 commands for fine tuning V0. These commands are VopOfsetInc (see section 8.1.43) and VopOfsetDec (see section 8.1.44). When writing VopOfsetInc into IC for each time, V0 would increase 40mV; when writing VopOfsetDec into IC for each time, V0 would decrease 40mV. Example: Vop [8:0] = 011010010 EV [6:0] = 0111111 VopOfsetInc x2 V0=3.6 + {210 + (63-63)} x 0.04 + 0.04x2 =12.08 (V) 7.9.2 Voltage Follower Circuits There is a build-in voltage follower circuits in ST7687A for generating Vg and Vm. These voltages are decided by bias ratio selection circuitry which is set by users with software to control 1/7 to 1/12 bias ratios to match the optimum display performance of LCD panel. Bias driving rule is listed below: LCD bias 1/N bias Vg (2/N) x V0 N=7 to 12 7.9.3 PROM Setting Flow ST7687A provides the Write and Read function to write the electronic control value and built-in resistance ratio into built-in PROM, and then read them from it. Using the Write and Read functions, you can store these values appropriate to each LCD panel. This function is very convenient for user in setting from some different panel's voltage. But using this function must attention the setting procedure. Please see the following diagram. Vm (1/N) x V0
Figure 10 V0 value control for different modules by loading PROM offset
Note1: This setting flow is used for LCM assembler. Note2: PROM shouldn't be written without preceding loading correctly from PROM in order to avoid some errors during IC operation. Note3: When writing value to PROM, the voltage of VPP must be 6.5V~6.75V; the current of Ivpp must be more than 8mA. Note4: If the PROM is exposed to a high temperature for hours, data in the memory cell may probably be lost before the data retention guarantee period. To retain data in the memory cell, keep the memory cell below 90. The data retention guarantee period is specified including the retention period.
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7.10 Frequency Temperature Gradient Compensation Coefficient
ST7687A will auto-switch frame rate on different temperature such as Figure 11. TA, TB and TC are frame rate switching temperatures which can be defined by customer with command TMPRNG (see section 8.1.60). FA, FB, FC and FD are switched frame rate which also can be defined by customer with command FRMSEL (see section 8.1.62). The frame rate range is from 38.8Hz to 194Hz. When the temperature is in increasing state, frame rate changes to the higher step at TA/TB/TC+TH (). When the temperature is in decreasing state, frame rate changes to the lower step at TA/TB/TC. For example: TC=10 and TH=5, FC switches to FD at 15 but FD switches to FC at 10. Please take Figure 11 for reference.
Figure 11 Relationship of Frequency and Temperature Compensation
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8
8.1
INSTRUCTIONS
Instruction Table Command Table
Hex Command A0
(00h) (01h) (09h) (0Ah) (0Bh) RDDMADCTR (0Ch) RDDCOLMOD (0Dh) (0Eh) (10h) (11h) (12h) (13h) (20h) (21h) (22h) SLPIN SLPOUT PTLON NORON INVOFF INVON APOFF RDDSM RDDIM RDDPM NOP SWRESET RDDST 0 0 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0
/RD /WR D7
1 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 -
D6
0 0 0 -
D5
0 0 0 -
D4
0 0 0 -
D3
0 0 1 -
D2
0 0 0 -
D1
0 0 0 -
D0
0 1 1 -
Function
No Operation Software reset Read Display Status Dummy read (D31-D24) (D23-D16) (D15-D8) (D7-D0) Read Display Power Mode Dummy read Read Display MADCTR Dummy read Read Display Pixel Format Dummy read Read Display Image Mode Dummy read Read Display signal Mode Dummy read Sleep in & booster off Sleep out & booster on Partial mode on Partial off (Normal)
Ref
8.1.1 8.1.2 8.1.3
ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST7 0 D7 0 D7 0 0 0 D7 0 D7 0 0 0 0 0 0 0 ST6 0 D6 0 D6 0 0 0 0 0 D6 0 0 0 0 0 0 0 ST5 0 D5 0 D5 0 0 0 D5 0 0 0 0 0 0 1 1 1 ST4 0 D4 0 D4 0 0 0 D4 0 0 1 1 1 1 0 0 0 ST3 1 D3 1 D3 1 0 1 D3 1 0 0 0 0 0 0 0 0 ST2 0 D2 0 0 1 D2 1 0 1 0 0 0 0 0 0 0 0 ST9 ST1 1 0 1 0 0 D1 0 0 1 0 0 0 1 1 0 0 1 ST8 ST0 0 0 1 0 0 D0 1 0 0 0 0 1 0 1 0 1 0
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9 8.1.10 8.1.11 8.1.12
Display inversion off (normal) 8.1.13 Display inversion on All pixel off (Only for test 8.1.15 purpose) 8.1.14
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Command Table
Hex Command A0
(23h) (25h) (28h) (29h) (2Ah) DISPOFF DISPON CASET APON WRCNTR 0 0 1 0 0 0 1 1 (2Bh) RASET 0 1 1 (2Ch) RAMWR 0 1 (2Eh) RAMRD 0 1 1 (30h) (33h) (34h) (35h) (36h) (37h) VSCSAD MADCTR TEOFF TEON SCRLAR PTLAR 0 1 1 0 1 1 1 0 0 1 0 1 0 1 (38h) (39h) (3Ah) IDMOFF IDMON COLMOD 0 0 0
/RD /WR D7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 D7 0 0 0 0 0 0 0 0 0 0 MY 0 0 0 0 0
D6
0 0 EV6 0 0 0 XS6 XE6 0 YS6 YE6 0 D6 0 D6 0 PS6 PE6 0
D5
1 1 EV5 1 1 1 XS5 XE5 1 YS5 YE5 1 D5 1 D5 1 PS5 PE5 1
D4
0 0 EV4 0 0 0 XS4 XE4 0 YS4 YE4 0 D4 0 D4 1 PS4 PE4 1
D3
0 0 EV3 1 1 1 XS3 XE3 1 YS3 YE3 1 D3 1 D3 0 PS3 PE3 0
D2
0 1 EV2 0 0 0 XS2 XE2 0 YS2 YE2 1 D2 1 D2 0 PS2 PE2 0
D1
1 0 EV1 0 0 1 XS1 XE1 1 YS1 YE1 0 D1 1 D1 0 PS1 PE1 1
D0
1
Function
All pixel on (Only for test
Ref
8.1.16
purpose) 1 EV0 0 1 0 XS0 XE0 1 YS0 YE0 0 D0 0 D0 Partial start/end address 0 setting PS0 PE0 1 Start address (0~127) End address (0~127) Scroll Area TFA=0~128 VSA=0~128 BFA=0~128 Tearing effect line off 8.1.26 8.1.25 8.1.24 Write contrast EV = 0 to 127 Display off Display on Column address set X_ADR start: 0XS7Fh X_ADR end: XSXE 7Fh Row address set Y_ADR start: 0YS7Fh Y_ADR end: YSYE7Fh Memory write Write data Memory Read Dummy read 8.1.23 8.1.22 8.1.21 8.1.18 8.1.19 8.1.20 8.1.17
TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 0 0 0 MX 0 1 1 1 MV 1 1 1 1 ML 1 0 0 0 RGB 0 1 1 1 1 0 0 1 1 0 1 M 0 1
Tearing effect mode set & on 8.1.27 "0": mode1, "1": mode2 Memory data access control 8.1.28 Scroll start address of RAM 8.1.29 SSA = 0~128 Idle mode off Idle mode on Interface pixel format 8.1.30 8.1.31 8.1.32
SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0
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Command Table
Hex Command A0
(DAh) (B0h) DutySet RDID 1 0 1 1 0 1 (B1h) FirstCom 0 1 (B3h) OscDiv 0 1 (B5h) NLInvSet 0 1
/RD /WR D7
1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 Du7 1 1 1 M
D6
1 0 0 Du6 0 F6 0 0 0
D5
0 0 1 Du5 1 F5 1 1 0
D4
1 0 1 Du4 1 F4 1 1 N4
D3
1 ID3 0 Du3 0 F3 0 0 N3
D2
P2 0 ID2 0 Du2 0 F2 0 1 N2
D1
P1 1 ID1 0 Du1 0 F1 1
D0
P0 0 ID0 0 Du0 1 F0 1
Function
Interface format Read ID Dummy read (D3-D0) Display Duty setting
Ref
8.1.33
8.1.34
First Com. Page address
8.1.35
FOSC divider
8.1.36
CLD1 CLD0 0 N1 1 N0 Com/Seg Scan Direction for N-line control 8.1.37
(B7h) ComScanDir
0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 1 0 1
0 SMX 0 0 0 0 1
1 0 1 1 1 0 0
1 0 1 1 1 0 0
0
1 0 0 0 1
1 0 0 0 0
1 Glass layout 0 0 1 1
8.1.38
SBGR
(B8h) (B9h)
RmwIn RmwOut
0 0 0 1
1 1 1 0 0
read modify write control IN 8.1.39 read modify write control Out 8.1.40 Display Compensation Step 8.1.41
(BDh) DispCompStep1
Step2 Step1 Step0 0 0 0 Vop setting 8.1.42
(C0h)
VopSet
0 1 1
Vop7 Vop6 Vop5 Vop4 Vop3 Vop2 Vop1 Vop0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 ID3 0 1 0 0 0 0 1 1 Vop8 1 0 1 +40mv/setp -40mv/setp Bias selection 8.1.43 8.1.44 8.1.45
(C1h)
VopOfsetInc
0 0 0 1
(C2h) VopOfsetDec (C3h) BiasSel
Bias2 Bias1 Bias0 1 0 0 Booster setting 8.1.46
(C4h) BstBmpXSel
0 1
BST2 BST 1 BST0 0 1 ID2 0 1 1 0 ID1 0 0 1 2BT0 0 ID0 0 1 Analog circuit setting 8.1.49 ID setting 8.1.48 FV3 with Booster x2 control 8.1.47
(CBh)
VgSorcSel
0 1
(CCh)
IDSet
0 1
(D0h)
ANASET
0 1
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Command Table
Hex Command A0
(D7h) AutoLoadSet 0 1 (E0h) EPCTIN 0 1 (E1h) (E2h) (E3h) (E4h) EPCOUT EPWR EPRD PROMSEL 0 0 0 0 1 (E5h) ROMSET 0 1 (ECh) DispCompStep2 0 1 (F0h) FRMSEL 0 1 1 1 1
/RD /WR D7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 MS1 1 0 1 0 1 -
D6
1 0 1 0 1 1 1 1 MS0 1 0 0 0 1 -
D5
0 1 0 1 1 1 1 0 1 0 1 0 1 -
D4
0 ARD 0
WR/RD
D3
0 1 0 0 0 0 0 0 1 0 1 1
D2
1 1 0 0 0 0 0 1 1 1 1 1
D1
1 1 0 0 0 1 1 0 0 0 1 0
D0
1
Function
PROM data auto re-load
Ref
8.1.50
control 1 0 0 1 0 1 0 1 1 1 1 Display Compensation Step 8.1.57 Programmable rom setting 8.1.56 PROM control out Write to PROM Read from PROM Select PROM 8.1.52 8.1.53 8.1.54 8.1.55 PROM control in 8.1.51
0 0 0 0 1 0 0 1 0 1 DIVA DIVB
Step3 Step2 Step1 Step0 Frame Freq. in Temp range 0 FA3 FB3 0 FA2 FB2 FC2 FD2 0 FA1 FB1 FC1 FD1 0 A,B,C and D FA0 FB0 FC0 FD0 Frame Freq. in Temp. range 8.1.58
DIVC FC3 DIVD FD3
(F1h)
FRM8SEL
0 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1
1 1 TA6 TB6 TC6 1 1
1 1 TA5 TB5 TC5 1 1
1
0
0
0
1 A,B,C and D (idle)
8.1.59
F8A4 F8A3 F8A2 F8A1 F8A0 F8B4 F8B3 F8B2 F8B1 F8B0 F8C4 F8C3 F8C2 F8C1 F8C0 F8D4 F8D3 F8D2 F8D1 F8D0 1 TA4 TB4 TC4 1 1 0 TA3 TB3 TC3 0 TH3 0 0 TA2 TB2 TC2 0 TH2 1 1 TA1 TB1 TC1 1 TH1 0 0 TA0 TB0 TC0 1 TH0 0 TEMPSEL 8.1.62 Hysteresis value set 8.1.61 Temp. range A,B and C 8.1.60
(F2h)
TMPRNG
0 1 1 1
(F3h)
TMPHYS
0 1
(F4h)
TEMPSEL
0 1 1
MT13 MT12 MT11 MT10 MT03 MT02 MT01 MT00 MT33 MT32 MT31 MT30 MT23 MT22 MT21 MT20
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Command Table
Hex Command A0
1 1 1 1 1 1
/RD /WR D7
1 1 1 1 1 1 0 0 0 0 0 0
D6
D5
D4
D3
D2
D1
D0
Function
Ref
MT53 MT52 MT51 MT50 MT43 MT42 MT41 MT40 MT73 MT72 MT71 MT70 MT63 MT62 MT61 MT60 MT93 MT92 MT91 MT90 MT83 MT82 MT81 MT80 MTB3 MTB2 MTB1 MTB0 MTA3 MTA2 MTA1 MTA0 MTD3 MTD2 MTD1 MTD0 MTC3 MTC2 MTC1 MTC0 MTF3 MTF2 MTF1 MTF0 MTE3 MTE2 MTE1 MTE0 Temperature detection
(F7h)
THYS
0 1
1 1 1 1 1 : 1 1
0 0 0 0 0 : 0 0
1
1
1
1
0
1
1
1 threshold
8.1.63
-
THYS6 THYS5 THYS4 THYS3 THYS2 THYS1 THYS0
(F9h)
Frame Set
0 1 1 : 1 1
1 : -
1 : -
1 : -
1 P14 P24 :
1 P13 P23 :
0 P12 P22 :
0 P11 P21 :
1 P10 P20 :
Set Frame RGB value
8.1.64
P154 P153 P152 P151 P150 P164 P163 P162 P161 P160
Note: During Sleep In mode, these commands are updated immediately. Read status (09H), Read Display Power Mode (0AH), Read Display MADCTR (0BH), Read Display Pixel Format (0CH), Read Display Image Mode (0DH), Read Display Signal Mode (0EH) of these commands is updated immediately both in Sleep In mode and Sleep Out mode
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8.1.1 NOP (00h) Command NOP A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Hex (00h)
This command is an empty command. It does not have effect on the display module. Description However it can be used to terminate RAM data write or read as described in RAMWR(Memory Write), RAMRD (Memory Read) and parameter write commands. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset Flow Chart N/A N/A N/A Yes Yes Yes Yes Yes Default Value Availability
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8.1.2 SWRESET: Software Reset (01h) Command SWRESET A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 Hex (01h)
When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all Description segment & common outputs are set to Vm (display off: blank display). (See default tables in each command description)
Note: The Frame Memory contents are not affected by this command.
It will be necessary to wait 5msec before sending new command following software reset. The display module loads all display suppliers' factory default Restriction values to the registers during 5msec. If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. Software Reset command cannot be sent during Sleep Out sequence. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset N/A N/A N/A Yes Yes Yes Yes Yes Default Value Availability
Flow Chart
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8.1.3 RDDST: Read Display Status (09h)
NOTE: "-" Don't care
Command RDDST Dummy Read 2nd parameter 3rd parameter 4th parameter 5th parameter
A0 0 1 1 1 1 1
/RD 1 0 0 0 0 0
/WR 0 1 1 1 1 1
D7 0 -
D6 0 -
D5 0 -
D4 0 -
D3 1 -
D2 0 -
D1 0 -
D0 1 -
Hex (09h) -
ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST8 ST0
This command indicates the current status of the display as described in the table below: Bit ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 Description Booster Voltage Status Row Address Order (MY) Column Address Order (MX) Row/Column Order (MV) Scan Address Order (ML) RGB/BGR Order (RGB) Not Used Not Used Not Used Interface Color Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status Not Used Inversion Status All Pixels On All Pixels Off Display On/Off Tearing effect line on/off Not Used Not Used Not Used Tearing effect line mode Not Used Not Used Not Used Not Used Value "1"=Booster on, "0"=off "1"=Decrement, "0"=Increment "1"=Decrement, "0"=Increment "1"= Row/column exchange (MV=1) "0"= Normal (MV=0) "1"=Decrement, "0"=Increment "1"=BGR, "0"=RGB "0" "0" "0" "011"=12 bit / pixel (type A) "100"=12 bit / pixel (type B) "101"=16-bit / pixel "1" = On, "0" = Off "1" = On, "0" = Off "1" = Out, "0" = In "1" = Normal Display, "0" = Partial "1" = Scroll on, "0" = Scroll off "0" "1" = On, "0" = Off "1" = all pixal on, "0" = normal display "1" = all pixal off, "0" = normal display "1" = On, "0" = Off "1" = On, "0" = Off "0" "0" "0" "0" = mode1, "1" = mode2 "0" "0" "0" "0"
Description
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ST0 Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset Yes Yes Yes Yes Yes Default Value (ST[31:0]) 0000 0000_0101 0001_0000 0000_0000 0000 0xxx xx00_0xxx 0001_0000 0000_0000 0000 0000 0000_0101 0001_0000 0000_0000 0000 Availability Not Used "0"
Serial I/F Mode
Read 09h
Parallel I/F Mode
Read 09h
Dummy Clock
Dummy Read
Legend
Command
Send 2nd parameter
Send 2nd parameter
Parameter
Flow Chart
Display Send 3rd parameter Send 3rd parameter Action
Send 4th parameter
Send 4th parameter
Mode
Send 5th parameter
Send 5th parameter
Sequential transter
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8.1.4 RDDPM: Read Display Power Mode (0Ah)
NOTE: "-" Don't care
Command RDDPM Dummy Read 2nd parameter
A0 0 1 1
/RD 1 0 0
/WR 0 1 1
D7 0 D7
D6 0 D6
D5 0 D5
D4 0 D4
D3 1 D3
D2 0 D2
D1 1 0
D0 0 0
Hex (0Ah) -
This command indicates the current status of the display as described in the table below: Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Booster Voltage Status Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Display On/Off Not Used Not Used Value "1"=Booster on, "0"=Booster off "1" = Idle Mode On, "0" = Idle Mode Off "1" = Partial Mode On, "0" = Partial "1" = Sleep Out, "0" = Sleep In "1" = Normal Display, "0" = Partial "1" = Display On, "0" = Display Off "0" "0"
Description
Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability
Status Default Power On Sequence S/W Reset H/W Reset
Default Value (D[7:0]) 00001000b (08h) 00001000b (08h) 00001000b (08h)
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8.1.5 RDDMADCTR: Read Display MADCTR (0Bh)
NOTE: "-" Don't care
Command RDDMADCTR Dummy Read 2nd parameter
A0 0 1 1
/RD 1 0 0
/WR 0 1 1
D7 0 D7
D6 0 D6
D5 0 D5
D4 0 D4
D3 1 D3
D2 0 0
D1 1 0
D0 1 0
Hex (0Bh) -
This command indicates the current status of the display as described in the table below: Bit D7 D6 Description D5 D4 D3 D2 D1 D0 Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability Description Row Address Order (MY) Column Address Order (MX) Row/Column Order (MV) Scan Address Order (ML) RGB/BGR Order (RGB) Not Used Not Used Not Used Value "1"=Decrement, "0"=Increment "1"=Decrement, "0"=Increment "1"= Row/column exchange (MV=1) "0"= Normal (MV=0) "1"=Decrement, "0"=Increment "1"=BGR, "0"=RGB "0" "0" "0"
Status Default Power On Sequence S/W Reset H/W Reset 00h No change 00h
Default Value (D[7:0])
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8.1.6 RDDCOLMOD: Read Display Pixel Format (0Ch)
NOTE: "-" Don't care
Command RDDCOLMOD Dummy Read 2nd parameter
A0 0 1 1
/RD 1 0 0
/WR 0 1 1
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 1 0
D2 1 D2
D1 0 D1
D0 0 D0
Hex (0Ch) -
This command indicates the current status of the display as described in the table below: Bit D7 D6 D5 D4 D3 D2 D1 D0 Description "0" (Not Used) "0" (Not Used) "0" (Not Used) "0" (Not Used) "0" "011"=12 bit/pixel (type A) "100"=12 bit/pixel (type B) "101"=16 bit/pixel Value
RGB Interface Color Format
Description
Control Interface Color Format
Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability
Status Default Power On Sequence S/W Reset H/W Reset 16 bit/pixel No change 16 bit/pixel
Default Value (D[2:0])
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8.1.7 RDDIM: Read Display Image Mode (0Dh)
NOTE: "-" Don't care
Command RDDIM Dummy Read 2nd parameter
A0 0 1 1
/RD 1 0 0
/WR 0 1 1
D7 0 D7
D6 0 0
D5 0 D5
D4 0 D4
D3 1 D3
D2 1 0
D1 0 0
D0 1 0
Hex (0Dh) -
This command indicates the current status of the display as described in the table below: Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Vertical Scrolling On/Off Not Used Inversion On/Off All Pixels On All Pixels Off Not Used Value "1" = Vertical scrolling is On, "0" = Vertical scrolling is Off, "0" "1" = Inversion is On, "0" = Inversion is "1" = All Pixels On, "0" = Normal Mode "1" = All Pixels Off, "0" = Normal Mode "0" "0" "0"
Description
Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability
Status Power On Sequence Default S/W Reset H/W Reset 00h 00h 00h
Default Value (D[7:0])
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8.1.8 RDDSM: Read Display Signal Mode (0Eh)
NOTE: "-" Don't care
Command RDDSM Dummy Read 2nd parameter
A0 0 1 1
/RD 1 0 0
/WR 0 1 1
D7 0 D7
D6 0 D6
D5 0 0
D4 0 0
D3 1 0
D2 1 0
D1 1 0
D0 0 0
Hex (0Eh) -
This command indicates the current status of the display as described in the table below: Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Tearing Effect Line On/Off Tearing effect line mode Not Used Not Used Not Used Not Used Not Used Not Used Value "1" = On, "0" = Off "0" = mode1, "1" = mode2 "0" "0" "0" "0" "0" "0"
Description
Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset 00h 00h 00h Yes Yes Yes Yes Yes Default Value (D[7:0]) Availability
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8.1.9 SLPIN: Sleep In (10h) Command SLPIN A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 Hex (10h)
This command causes the LCD module to enter the minimum power consumption mode. Description In this mode e.g. the DC/DC converter, Internal oscillator, and panel scanning are all stopped. MCU interface and memory are still working and the memory keeps its contents. This command has no effect when module is already in sleep in mode. Sleep In Mode can only be left by the Sleep Out Command (11h). Restriction It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode Availability
Flow Chart
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8.1.10 SLPOUT: Sleep Out (11h) Command SLPOUT A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 Hex (11h)
Description
This command turns off sleep mode. In this mode e.g. the DC/DC converter is enabled, Internal oscillator is started, and panel scanning is started. 1. This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be left by the Sleep In Command (10h). 2. It will be necessary to wait 5msec before sending next command; this is to allow time for the supply voltages and clock circuits to stabilize.
Restriction
3. The display module loads all display supplier's factory default values to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if factory default and register values are same when this load is done and when the display module is already Sleep Out -mode. 4. There is the 250ms no display period if the state is exited from sleep in mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset
Default Value Sleep in mode Sleep in mode Sleep in mode
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8.1.11 PTLON: Partial Display Mode On (12h) Command PTLON A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 Hex (12h)
This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H) Description Exit from PTLON by Normal Display Mode On command (13H) There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. Restriction This command has no effect when Partial mode is active. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability
Status Default Power On Sequence S/W Reset H/W Reset Flow Chart See Partial Area (30h)
Default Value Partial mode off Partial mode off Partial mode off
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8.1.12 NORON: Normal Display Mode On (13h) Command NORON A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 1 Hex (13h)
This command returns the display to normal mode. Normal display mode on means Partial mode off, Scroll mode Off. Description Exit from NORON by the Partial mode On command (12h) There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. Restriction This command has no effect when Normal Display mode is active. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Yes Yes Yes Yes Yes Default Value Normal Mode On Normal Mode On Normal Mode On Availability
Flow Chart
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command
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8.1.13 INVOFF: Display Inversion Off (20h) Command INVOFF A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 Hex (20h)
This command is used to recover from display inversion mode. This command makes no change of contents of frame memory. This command does not change any other status.
Description
Restriction
This command has no effect when module is already inversion off mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Status Power On Sequence Default Value Display Inversion off Display Inversion off Display Inversion off Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
S/W Reset H/W Reset
Display Inversion On Mode
Flow Chart
INVOFF
Display Inversion Off Mode
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8.1.14 INVON: Display Inversion On (21h) Command INVON A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 Hex (21h)
This command is used to enter into display inversion mode This command makes no change of contents of frame memory. This command does not change any other status. To exit from Display Inversion On, the Display Inversion Off command (20h) should be written. Description
Restriction
This command has no effect when module is already Inversion On mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Status Power On Sequence Default Value Display Inversion off Display Inversion off Display Inversion off Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
S/W Reset H/W Reset
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Display Inversion Off Mode
Flow Chart
INVON
Display Inversion On Mode
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8.1.15 APOFF: All Pixels Off (22h) (Only for Test Purposes) Command APOFF A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Hex (22h)
This command is only used for test purpose e.g. pixel response time (on/off) measurements on the passive matrix display. Therefore, it is possible that this command is not used for final product software. All driver outputs become "Low" data state and display becomes black. This command makes no change of contents of display memory. This command does not change any other status. Exit commands are "All Pixels On", "Normal Display Mode On" and "Partial Display On". Description The display is showing the contents of the frame memory after "Normal Display Mode On" and "Partial Display On" commands.
Restriction
This command has no effect when module is already All Pixel Off mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Default Value All pixel off mode disable All pixel off mode disable All pixel off mode disable Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence
Default
S/W Reset H/W Reset
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8.1.16 APON: All Pixels On (23h) (Only for Test Purposes) Command APON A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 Hex (23h)
This command is only used for test purpose e.g. pixel response time (on/off) measurements on the passive matrix display. Therefore, it is possible that this command is not used for final product software. All driver outputs become "High" data state and display becomes white. This command makes no change of contents of display memory. This command does not change any other status. Exit commands are "All Pixels On", "Normal Display Mode On" and "Partial Display On". Description The display is showing the contents of the frame memory after "Normal Display Mode On" and "Partial Display On" commands.
Restriction
This command has no effect when module is already All Pixel On mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset
Default Value All pixel on mode disable All pixel on mode disable All pixel on mode disable
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8.1.17 WRCNTR: Write Contrast (25h)
NOTE: "-" Don't care
Command WRCNTR Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 0 0
D6 0 EV6
D5 1 EV5
D4 0 EV4
D3 0 EV3
D2 1 EV2
D1 0 EV1
D0 1 EV0
Hex (25h) -
This command is used to fine tuning the contrast of the display. Parameter range is Description 00~7Fh. The contrast is not linear but the contrast adjustment is linear. Luminance is increasing from 00h to 7Fh. 00h is presenting dark end and 7Fh is presenting bright end. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability
Status Power On Sequence Default S/W Reset H/W Reset 3Fh 3Fh 3Fh
Default Value
Legend
Command
WRCNTR
Parameter
Display
Flow Chart
EV[7:0]
Action
Mode
New Contrast Value Loaded
Sequential transter
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8.1.18 DISPOFF: Display Off (28h) Command DISPOFF A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 Hex (28h)
This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory disables and blank page inserted. This command makes no change of contents of frame memory. This command does not change any other status. There will be no abnormal visible effect on the display. Description Exit from this command by Display On (29h)
Restriction
This command has no effect when module is already in Display Off mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset Display off Display off Display off
Default Value
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Display On Mode
Flow Chart
DISPOFF
Display Off Mode
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8.1.19 DISPON: Display On (29h) Command DISPON A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 Hex (29h)
Turn on the display screen according to the current display data RAM content and the display timing and setting. This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. This command makes no change of contents of frame memory. Description This command does not change any other status.
Restriction
This command has no effect when module is already in Display On mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset Display off Display off Display off
Default Value
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Display Off Mode
Flow Chart
DISPON
Display On Mode
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8.1.20 CASET: Column Address Set (2Ah)
NOTE: "-" Don't care
Command CASET 1st Parameter 2nd Parameter
A0 0 1 1
/RD 1 1 1
/WR 0 0 0
D7 0 0 0
D6 0 XS6 XE6
D5 1 XS5 XE5
D4 0 XS4 XE4
D3 1 XS3 XE3
D2 0 XS2 XE2
D1 1 XS1 XE1
D0 0 XS0 XE0
Hex (2Ah) -
This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory.
Description
Restriction
XS [6:0] always must be equal to or less than XE [6:0] When XS [6:0] or XE [6:0] is greater than 7Fh, data of out of range will be ignored. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Default Value XS [6:0] XE [6:0] 7Fh 7Fh 7Fh Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset
00h 00h 00h
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CASET
1st parameter XS[6:0] 2nd parameter XE[6:0]
Legend
PASET Command
Flow Chart
1st parameter YS[6:0] 2nd parameter YE[6:0]
Parameter
Display
RAMWR Action
Image Data D1[7:0],D2[7:0] .......Dn[7:0]
Mode
Sequential transter Any Command
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8.1.21 RASET: Row Address Set (2Bh)
NOTE: "-" Don't care
Command RASET 1st Parameter 2nd Parameter
A0 0 1 1
/RD 1 1 1
/WR 0 0 0
D7 0 0 0
D6 0 YS6 YE6
D5 1 YS5 YE5
D4 0 YS4 YE4
D3 1 YS3 YE3
D2 0 YS2 YE2
D1 1 YS1 YE1
D0 1 YS0 YE0
Hex (2Bh) -
This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of YS [6:0] and YE [6:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory.
Description
Restriction
YS [6:0] always must be equal to or less than YE [6:0] When YS [6:0] or YE [6:0] is greater than 7Fh, data of out of range will be ignored. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset 00h 00h 00h
Default Value XS [6:0] XE [6:0] 7Fh 7Fh 7Fh
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CASET
1st parameter XS[6:0] 2nd parameter XE[6:0]
Legend
Command
PASET
Parameter
Flow Chart
1st parameter YS[6:0] 2nd parameter YE[6:0]
Display
Action
RAMWR
Image Data D1[7:0],D2[7:0] .......Dn[7:0]
Mode
Sequential transter
Any Command
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8.1.22 RAMWR: Memory Write (2Ch) Command RAMWR Write D1[7:0] : Write Dn[7:0] A0 0 1 1 1 /RD 1 1 1 1 /WR 0 0 0 0 D7 0 D7 : D7 D6 0 D6 : D6 D5 1 D5 : D5 D4 0 D4 : D4 D3 1 D3 : D3 D2 1 D2 : D2 D1 0 D1 : D1 D0 0 D0 : D0 Hex (2Ch) -
This command is used to transfer data MCU to frame memory. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Description Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTR setting. Then D[7:0] is stored in frame memory and the column register and the row register incremented. Frame Write can be canceled by sending any other command. Restriction In all color modes, there is no restriction on length of parameters. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is remained Contents of memory is remained Availability
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8.1.23 RAMRD: Memory Read (2EH)
NOTE: "-" Don't care
Command RAMRD Dummy read 2nd parameter ... (N+1)th parameter
A0 0 1 1 1 1
/RD 1 0 0 0 0
/WR 0 1 1 1 1
D7 0 D17 Dx7 Dn7
D6 0 D16 Dx6 Dn6
D5 1 D15 Dx5 Dn5
D4 0 D14 Dx4 Dn4
D3 1 D13 Dx3 Dn3
D2 1 D12 Dx2 Dn2
D1 1 D11 Dx1 Dn1
D0 0 D10 Dx0 Dn0
HEX (2Eh) 00H ~ FFH 00H ~ FFH 00H ~ FFH
This command is used to transfer data from frame memory to MCU. When this command is accepted, the column register and the page register are reset to the Start Column/Start Page Description positions. The Start Column/Start Page positions are different in accordance with MADCTR setting. Then D [7:0] is read back from the frame memory and the column register and the page register incremented. Frame Read can be stopped by sending any other command. Restriction In all color modes, the Frame Read is always 16bit so there is no restriction on length of parameters. Note: Memory Read is only possible via the Parallel Interface.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off
Availability Yes Yes Yes Yes Yes
Status Power On Sequence Default S/W Reset H/W Reset
Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
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Legend
RAMRD
Command
Parameter
Dummy
Display
Flow Chart
Action
Image Data D1[7:0],D2[7:0] ........Dn[7:0]
Mode
Sequential transter
Any Command
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8.1.24 PTLAR: Partial Area (30h)
NOTE: "-" Don't care
Command PTLAR 1st Parameter 2nd Parameter
A0 0 1 1
/RD 1 1 1
/WR 0 0 0
D7 0 0 0
D6 0 PS6 PE6
D5 1 PS5 PE5
D4 1 PS4 PE4
D3 0 PS3 PE3
D2 0 PS2 PE2
D1 0 PS1 PE1
D0 0 PS0 PE0
Hex (30h) -
This command defines the partial mode's display area. There are 2 parameters associated with this command, the first defines the Start Line (PS) and the second the End Line (PE), as illustrated in the figures below. PS and PE refer to the Frame Memory Line counter. If End Line > Start Line when MADCTR ML=0:
Description If End Line > Start Line when MADCTR ML=1:
If End Line < Start Line when MADCTR ML=0:
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* Row1: Frame memory row address 1. If End Line = Start Line then the Partial Area will be one line deep. PS[6:0] and PE[6:0] are based on line unit. Restriction PS[6:0]=00h, 01h, 02h, 03h, ... , 7Fh PE[6:0]= 00h, 01h, 02h, 03h, ... , 7Fh Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Default Value Status PS[6:0] Default Power On Sequence S/W Reset H/W Reset 00h 00h 00h 7Fh 7Fh 7Fh PE[6:0] Availability
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8.1.25 SCRLAR: Scroll Area (33h)
NOTE: "-" Don't care
Command SCRLAR 1st parameter 2nd parameter 3rd parameter
A0 0 1 1 1
/RD 1 1 1 1
/WR 0 0 0 0
D7 0
D6 0
D5 1
D4 1
D3 0
D2 0
D1 1
D0 1
Hex (33h) -
TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
This command just defines the Vertical Scrolling Area of the display and not performs vertical scroll. When MADCTR ML=0 The 1st parameter TFA [7:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). The 2nd parameter VSA [7:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area. The 3rd parameter BFA [7:0] describes the Bottom Fixed Area (in No. of lines from Bottom of Descriptio n the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer.
Restriction
The condition is (TFA+VSA+BFA) = 128, otherwise Scrolling mode is undefined. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
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Default Value Status TFA [7:0] Default Power On Sequence S/W Reset H/W Reset 00h 00h 00h VSA [7:0] 80h 80h 80h BFA [7:0] 00h 00h 00h
Flow Chart
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
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Flow Chart
NOTE: Scroll Mode can be exit by both the Normal Display Mode On (13h) and Partial Mode On (12h) commands.
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8.1.26 TEOFF: Tearing Effect Line OFF (34h) Command TEOFF A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 Hex (34h)
Description Restriction
This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. This command has no effect when Tearing Effect output is already OFF. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset
Default Value Tearing effect off Tearing effect off Tearing effect off
Flow Chart
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8.1.27 TEON: Tearing Effect Line ON (35h)
NOTE: "-" Don't care
Command TEON Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 0 -
D6 0 -
D5 1 -
D4 1 -
D3 0 -
D2 1 -
D1 0 -
D0 1 M
Hex (35h) -
This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTR bit ML. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. ("-"=Don't Care). When M=0: The Tearing Effect Output Line consists of V-Blanking information only:
Description
When M=1: The Tearing Effect Output Line consists of both V-Blanking and H-Blanking information:
See section 7.4.8 for more information.
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Restriction
This command has no effect when Tearing Effect output is already OFF. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Power On Sequence Default S/W Reset H/W Reset
Default Value Tearing effect off & M=0 Tearing effect off & M=0 Tearing effect off & M=0
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8.1.28 MADCTR: Memory Data Access Control (36h)
NOTE: "-" Don't care
Command MADCTR Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 0 MY
D6 0 MX
D5 1 MV
D4 1 ML
D3 0 RGB
D2 1 -
D1 1 -
D0 0 -
Hex (36h) -
This command defines read/write scanning direction of frame memory. This command makes no change on the other driver status. Note: ML affects to Partial Area (30h), Vertical Scrolling Definition (33h), Vertical Scrolling Start address (37h), Partial On (12h) commands Bit Assignment Bit MY MX MV ML NAME ROW ADDRESS ORDER COLUMN ADDRESS ORDER ROW/COLUMN ORDER LINE ADDRESS ORDER LCD refresh direction control Color selector switch control Description RGB RGB-BGR ORDER 0=RGB color filter panel, 1=BGR color filter panel The contents of the frame memory are not changed. These 3bits controls MCU to memory write/read direction. DESCRIPTION
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Restriction
D2, D1 and D0 of the 1st parameter are set to `000'internally. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Power On Sequence Default S/W Reset H/W Reset
Default Value MY=0,MX=0,MV=0,ML=0,RGB=0 Not changed MY=0,MX=0,MV=0,ML=0,RGB=0
Legend
Command
Parameter
Display
Flow Chart
Action
Mode
Sequential transter
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8.1.29 VSCSAD: Vertical Scroll Start Address of RAM (37h)
NOTE: "-" Don't care
Command VSCSAD Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 0 0
D6 0
D5 1
D4 1
D3 0
D2 1
D1 1
D0 1
Hex (37h) -
SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0
This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: This command Start the scrolling. Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h). When MADCTR ML=0 Example: When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=128 and Vertical Scrolling Pointer SSA='3'.
Description
When MADCTR ML=1 Example: When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=128 and Vertical Scrolling Pointer SSA='3'.
NOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. SSA refers to the Frame Memory line Pointer.
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Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition Restriction (33h)-otherwise undesirable image will be displayed on the Panel. SSA [6:0] is based on line unit. SSA [6:0] = 00h, 01h, 02h, 03h, ... , 7Fh
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes No No Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset Flow Chart 00h 00h 00h
Default Value (SSA[6:0])
See Vertical Scrolling Definition (33h) description.
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8.1.30 IDMOFF: Idle Mode Off (38h) Command IDMOFF A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 Hex (38h)
This command is used to recover from Idle mode on. There will be no abnormal visible effect on the display mode change transition. Description In the idle off mode, 1. LCD can display maximum 65,536 colors. 2. Normal frame frequency is applied. Restriction This command has no effect when module is already in idle off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset
Default Value Idle mode off Idle mode off Idle mode off
Flow Chart
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8.1.31 IDMON: Idle Mode On (39h) Command IDMON A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 Hex (39h)
This command is used to enter into Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R, G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command
Description
"X": don't care
Color Black Blue Red Magenta Green Cyan Yellow White Restriction
R4 R3 R2 R1 R0 0XXXX 0XXXX 1XXXX 1XXXX 0XXXX 0XXXX 1XXXX 1XXXX
G5 G4 G3 G2 G1 G0 0XXXXX 0XXXXX 0XXXXX 0XXXXX 1XXXXX 1XXXXX 1XXXXX 1XXXXX
B4 B3 B2 B1 B0 0XXXX 1XXXX 0XXXX 1XXXX 0XXXX 1XXXX 0XXXX 1XXXX
This command has no effect when module is already in idle on mode. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
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Status Default Power On Sequence S/W Reset H/W Reset Default Value Idle mode off Idle mode off Idle mode off
Flow Chart
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8.1.32 COLMOD: Interface Pixel Format (3Ah)
NOTE: "-" Don't care
Command COLMOD Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 0 -
D6 0 -
D5 1 -
D4 1 -
D3 1 -
D2 0 P2
D1 1 P1
D0 0 P0
Hex (3Ah) -
This command is used to define the format of RGB picture data, which is to be transferred via the MCU Interface. The formats are shown in the table: Interface Format Not Defined Not Defined Description Not Defined 12Bit/Pixel (Type A) 12Bit/Pixel (Type B) 16Bit/Pixel Not Defined Not Defined Restriction P2 0 0 0 0 1 1 1 1 P1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1
There is no visible effect until the Frame Memory is written to. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Power On Sequence Default S/W Reset H/W Reset
Default Value 05h (16Bit/Pixel) No Change 05h (16Bit/Pixel)
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8.1.33 RDID: Read ID Value (DAh)
NOTE: "-" Don't care
Command RDID Dummy Read 2nd parameter
A0 0 1 1
/RD 1 0 0
/WR 0 1 1
D7 1 0
D6 1 0
D5 0 0
D4 1 0
D3 1 ID3
D2 0 ID2
D1 1 ID1
D0 0 ID0
Hex (DAh) -
Description Restriction
This read byte returns 8-bit LCD module's manufacturer ID D3-D0 (ID3 to ID0): LCD module's manufacturer ID.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset 00h 00h 00h
Default Value
Flow Chart
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8.1.34 DutySet: Display Duty setting (B0H)
NOTE: "-" Don't care
Command DutySet Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 Du7
D6 0 Du6
D5 1 Du5
D4 1 Du4
D3 0 Du3
D2 0 Du2
D1 0 Du1
D0 0 Du0
Hex (B0h) -
This command is used to set display duty. Command set = display duty numbers - 1. Example: Command set= Description Duty Du7 Du6 Du5 Du4 Du3 Du2 Du1 Du0 Display duty numbers-1 1/128 duty Restriction 0 1 1 1 1 1 1 1 128-1=127
Display duty must > 4 (1/4 duty) Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset Flow Chart
Default Value 0111111b (7Fh) 0111111b (7Fh) 0111111b (7Fh)
(Du[6:0])
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DutySet
Du[7:0]
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8.1.35 FirstCom: First Com. Page address (B1H)
NOTE: "-" Don't care
Command FirstCom Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 0
D6 0 F6
D5 1 F5
D4 1 F4
D3 0 F3
D2 0 F2
D1 0 F1
D0 1 F0
Hex (B1h) -
This command defines the first output COM number that mapping to the RAM page address 0. For detail setting value, please see the table as below. F6 0 0 0 0 : 1 Example: If FirstCom=8, common 8 would output the data of RAM page address 0. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability F5 0 0 0 0 : 1 F4 0 0 0 0 : 1 F3 0 0 1 1 : 1 F2 F1 F0 0 1 0 1 : 1 Line address 0 1 2 3 : 127
Description
1
1
Status Default Power On Sequence S/W Reset H/W Reset 00h 00h 00h
Default Value
(F[6:0])
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Flow Chart
F[6:0]
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8.1.36 OscDiv: FOSC Divider (B3H)
NOTE: "-" Don't care
Command OscDiv Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 -
D6 0 -
D5 1 -
D4 1 -
D3 0 -
D2 0 -
D1 1
D0 1
Hex (B3h) -
CLD1 CLD0
This command is used to specify the Fosc dividing ratio. CLD1, CLD0: CL dividing ratio. They are used to change number of dividing stages of internal clock. CLD1 Description 0 0 1 1 Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Yes Yes Yes Yes Yes Default Value 00b 00b 00b (CLD[0:1]) Availability CLD0 0 1 0 1 Fosc dividing ratio Not divide 2 divisions 4 divisions 8 divisions
OscDiv
Flow Chart
CLD[1:0]
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8.1.37 NLInvSet: N-Line control (B5H)
NOTE: "-" Don't care
Command NLInvSet Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 M
D6 0 0
D5 1 0
D4 1 N4
D3 0 N3
D2 1 N2
D1 0 N1
D0 1 N0
Hex (B5h) -
This command is used to set the inverted line number with range of 2 to (duty-1) to improve display quality. When M=0, inversion occurs in every frame; when M=1, inversion is Description independent from frames. If N[4:0] =0, N-line inversion function is disable. Line inversion numbers=N[4:0] +1. Example: If N[4:0]=7, inversion occurs per 8 line. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Default Value M Default Power On Sequence S/W Reset H/W Reset 0b 0b 0b N[4:0] 00000b 00000b 00000b Availability
Status
NLInvSet
Flow Chart
M & N[4:0]
Ver. 1.0
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8.1.38 ComScanDir: Com/Seg Scan Direction for glass layout (B7H)
NOTE: "-" Don't care
Command ComScanDir Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 0
D6 0 SMX
D5 1 0
D4 1 0
D3 0 SBGR
D2 1 0
D1 1 0
D0 1 0
Hex (B7h) -
Bit Description SMX SBGR Restriction
Function Inverse the MX setting Inverse the BGR setting
0 Keep MX Keep BGR
1 Inverse MX Inverse BGR
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset 40h 40h 40h
Default Value
ComScanDir
Flow Chart
SMX & SBGR
Ver. 1.0
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8.1.39 RMWIN: Read Modify Write control in (B8H) Command RMWIN A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 Hex (B8h)
Description Restriction
Read modify write control in.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset ---Yes Yes Yes Yes Yes
Availability
Default Value
Ver. 1.0
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8.1.40 RMWOUT: Read Modify Write control out (B9H) Command RMWOUT A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 Hex (B9h)
Description Restriction
Read modify write control out
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset ---Yes Yes Yes Yes Yes
Availability
Default Value
Ver. 1.0
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8.1.41 DispCompStep1: Display Compensation Step1 (BDH)
NOTE: "-" Don't care
Command DispCompStep1 Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 0
D6 0 0
D5 1 0
D4 1 0
D3 1 0
D2 1
D1 0
D0 1
Hex (BDh) -
Step2 Step1 Step0
Description Restriction
The command is used to program the optimum LCD display quality. Step2 0 0 0 0 1 1 1 1 Step1 0 0 1 1 0 0 1 1 Step0 0 1 0 1 0 1 0 1 STEP 1 2 3 4 5 6 7 8
Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Power On Sequence S/W Reset H/W Reset 04h 04h 04h Default Value Yes Yes Yes Yes Yes Availability
Ver. 1.0
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8.1.42 VopSet: Vop set (C0H)
NOTE: "-" Don't care
Command VopSet 1 parameter 2 parameter
nd st
A0 0 1 1
/RD 1 1 1
/WR 0 0 0
D7 1
D6 1
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Hex (C0h) -
Vop7 Vop6 Vop5 Vop4 Vop3 Vop2 Vop1 Vop0 Vop8
Description
The command is used to program the optimum LCD supply voltage V0. Please see Section 7.9 for reference.
Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default Status Default Value (Vop=12V) Vop8 Power On Sequence S/W Reset H/W Reset Flow Chart 0 0 0 Vop[7:0] 11010010b (D2h) 11010010b (D2h) 11010010b (D2h) Yes Yes Yes Yes Yes Availability
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8.1.43 VopOfsetInc: Vop Increase 1 (C1H)
NOTE: "-" Don't care
Command VopOfsetInc
A0 0
/RD 1
/WR 0
D7 1
D6 1
D5 0
D4 0
D3 0
D2 0
D1 0
D0 1
Hex (C1h)
With the VopOfsetInc and VopOfsetDec command the VLCD voltage and therewith the contrast of the LCD can be adjusted. This command increases the value of Vop offset Description register by 1. If you set the electronic control value to 1111111, the control value is set to 0000000 after this command has been executed. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability
Status Default Power On Sequence S/W Reset H/W Reset ----
Default Value
Flow Chart
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8.1.44 VopOfsetDec: Vop Decrease 1 (C2H)
NOTE: "-" Don't care
Command VopOfsetDec
A0 0
/RD 1
/WR 0
D7 1
D6 1
D5 0
D4 0
D3 0
D2 0
D1 1
D0 0
Hex (C2h)
With the VopOfsetInc and VopOfsetDec command the VLCD voltage and therewith the contrast of the LCD can be adjusted. This command decreases the value of Vop offset register by 1. If you set the electronic control value to 0000000, the control value is set to 1111111 after this command has been executed.
Electronic Control Value 0111111 0111110 0111101 Description ... 0000010 0000001 0000000 1111111 1111110 ... 1000010 1000001 1000000
Decimal Equivalent 63 62 61 ... 2 1 0 -1 -2 ... -62 -63 -64
V0 Offset +2520 mV +2480 mV +2440 mV ... +80 mV +40 mV 0 mV -40 mV -80 mV ... -2440 mV -2480 mV -2520 mV
Possible Vop offset [6:0] values Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability
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Status Default Power On Sequence S/W Reset H/W Reset ---Default Value
Flow Chart
Ver. 1.0
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8.1.45 BiasSel: Bias Selection (C3H)
NOTE: "-" Don't care
Command BiasSel Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 -
D6 1 -
D5 0 -
D4 0 -
D3 0 -
D2 0
D1 1
D0 1
Hex (C3h) -
Bias2 Bias1 Bias0
Select LCD bias ratio of the voltage required for driving the LCD. Bais2 0 0 0 Description 0 1 1 1 1 Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Yes Yes Yes Yes Yes Default Value 011b 011b 011b (Bias[2:0]) Availability Bais1 0 0 1 1 0 0 1 1 Bais0 0 1 0 1 0 1 0 1 LCD bias 1/12 1/11 1/10 1/9 1/8 1/7 Reserved Reserved
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Flow Chart
Ver. 1.0
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8.1.46 BstPmpXSel: Booster Setting (C4H)
NOTE: "-" Don't care
Command BstPmpXSel Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 -
D6 1 -
D5 0 -
D4 0 -
D3 0 -
D2 1
D1 0
D0 0
Hex (C4h) -
BST2 BST 1 BST0
Booster setting BST2 0 0 Description 0 0 1 1 1 1 Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset 111b 111b 111b Yes Yes Yes Yes Yes Default Value (BST[2:0]) Availability BST1 BST0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description Reserved Reserved Reserved Reserved x5 boosting circuit x6 boosting circuit x7 boosting circuit x8 boosting circuit
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Flow Chart
Ver. 1.0
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8.1.47 VgSorcSel: Vg source control (CBH)
NOTE: "-" Don't care
Command VgSorcSel Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 -
D6 1 -
D5 0 -
D4 0 -
D3 1 -
D2 0 -
D1 1 -
D0 1 2BT0
Hex (CBh) -
Description Restriction
2BT0=0: Vg source comes from VDD2 ; 2BT0=1: Vg source comes from 2-times charge pump.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset 1 1 1 Yes Yes Yes Yes Yes
Availability
Default Value (2BT0)
Legend
Command
Parameter
Display
Flow Chart
Action
Mode
Sequential transter
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8.1.48 IDSet: ID setting (CCH)
NOTE: "-" Don't care
Command IDSet Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 0
D6 1 0
D5 0 0
D4 0 0
D3 1 ID3
D2 1 ID2
D1 0 ID1
D0 0 ID0
Hex (CCh) -
Description Restriction
ID setting for request by customer
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Power On Sequence Default S/W Reset H/W Reset 00h 00h 00h
Default Value
Legend
Command
Parameter
Display
Flow Chart
Action
Mode
Sequential transter
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8.1.49 NASET: Analog circuit setting (D0H)
NOTE: "-" Don't care
Command NASET Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 -
D6 1 0
D5 0 0
D4 1 1
D3 0 1
D2 0 1
D1 0 0
D0 0 1
Hex (D0h) (1Dh)
Description Restriction
Analog circuit setting. Such as follower selection, level shifter power mode selection.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset Yes Yes Yes Yes Yes
Availability
Default Value D[7:0] 19H 19H 19H
Flow Chart
Ver. 1.0
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8.1.50 AutoLoadSet: PROM data auto re-load control (D7H)
NOTE: "-" Don't care
Command AutoLoadSet Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 1
D6 1 0
D5 0 0
D4 1 ARD
D3 0 1
D2 1 1
D1 1 1
D0 1 1
Hex (D7h) -
Description Restriction
ARD : PROM auto read enable control, 1: Disable PROM auto read, 0: Enable PROM auto read
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset
Default ValueD[7:0] 8FH 8FH 8FH
Legend
Command
Parameter
Display
Flow Chart
Action
Mode
Sequential transter
Ver. 1.0
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8.1.51 EPCTIN: Control PROM WR/RD (E0H)
NOTE: "-" Don't care
Command EPCTIN Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 0
D6 1 0
D5 1 WR /XRD
D4 0 0
D3 0 0
D2 0 0
D1 0 0
D0 0 0
Hex (E0h) -
Description Restriction
WR/XRD: when setting "1", the Write enable of PROM will be opened. WR/XRD: when setting "0", the Read enable of PROM will be opened.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset 0 0 0
Default Value
Flow Chart
Ver. 1.0
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8.1.52 EPCOUT: PROM control out (E1H)
NOTE: "-" Don't care
Command EPCOUT
A0 0
/RD 1
/WR 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 0
D0 1
Hex (E1h)
Description Restriction
IC exits the PROM control circuit when executing this command.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset ----
Default Value
PROMSEL
Legend
Command
MS[1:0]
Parameter
EPCTIN
Display
Flow Chart
WR/XRD=1
Action
EPMWR
Mode
Sequential transter
EPCOUT
Ver. 1.0
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8.1.53 EPWR: Write to PROM (E2H) Command EPWR A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Hex (E2h)
Description Restriction
IC actives trigger to start PROM programming when executing this command.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset ----
Default Value
PROMSEL
MS[1:0]
EPCTIN
Flow Chart
WR/XRD=1
EPWR
EPCOUT
Ver. 1.0
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8.1.54 EPRD: Read from PROM (E3H)
NOTE: "-" Don't care
Command EPRD
A0 0
/RD 1
/WR 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 1
D0 1
Hex (E3h)
Description Restriction
IC actives trigger to start PROM data download to circuit when executing this command.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset ----
Default Value
Flow Chart
Ver. 1.0
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8.1.55 PROMSEL: SEL PROM (E4H)
NOTE: "-" Don't care
Command PROMSEL Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1
D6 1
D5 1 0
D4 0 1
D3 0 1
D2 1 0
D1 0 0
D0 0 0
Hex (E4h) -
MS1 MS0
This command defines PROM selection control. Please see the table as below: MS1 Description 0 0 Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes Availability 0 1 Disable PROM MS0 Mode
Status Default Power On Sequence S/W Reset H/W Reset 18h 18h 18h
Default Value D[7:0]
Flow Chart
Ver. 1.0
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8.1.56 ROMSET: Programmable rom setting (E5H)
NOTE: "-" Don't care
Command ROMSET Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 0
D6 1 0
D5 1 0
D4 0 0
D3 0 1
D2 1 1
D1 0 1
D0 1 1
Hex (E5h) -
Description Restriction
Set the PROM writing timing.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset
Default Value D[7:0] 0Fh 0Fh 0Fh
Flow Chart
Ver. 1.0
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8.1.57 DispCompStep2: Display Compensation Step2(ECH)
NOTE: "-" Don't care
Command DispCompStep2 Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 0
D6 1 0
D5 1 0
D4 0 0
D3 1
D2 1
D1 0
D0 0
Hex (ECh) -
Step3 Step2 Step1 Step0
Description
The command is used to program the optimum LCD display quality. Step3 0 0 0 0 0 0 0 Step2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Step1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Step0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Restriction
0 1 1 1 1 1 1 1 1
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Power On Sequence Default S/W Reset H/W Reset 04h 04h 04h
Default Value
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8.1.58 FRMSEL: Frame Freq. in Temperature range (F0H)
NOTE: "-" Don't care
Command FRMSEL 1 parameter 2 parameter 3 parameter 4 parameter
th rd nd st
A0 0 1 1 1 1
RD 1 1 1 1 1
WR 0 0 0 0 0
D7 1 -
D6 1 -
D5 1 -
D4 1 DIVA DIVB DIVC DIVD
D3 0 FA3 FB3 FC3 FD3
D2 0 FA2 FB2 FC2 FD2
D1 0 FA1 FB1 FC1 FD1
D0 0 FA0 FB0 FC0 FD0
HEX (F0H) Range A Range B Range C Range D
Select Frame Freq. in normal display mode. 1 parameter : Frame freq. value set in temperature range -40 to TA 2 parameter : Frame freq. value set in temperature P range TA to TB 3 parameter : Frame freq. value set in temperature range TB to TC 4 parameter : Frame freq. value set in temperature range TC to 87 For command setting to frame rate value look-up-table, please see the following table:
th rd nd st
DIVx Fx[3:0] 0 1 2 Description 3 4 5 6 1 7 8 9 A B C D E F
1 Frame Rate (Hz) 77.6 77.6 77.6 77.6 77.6 97 97 97 97 97 129.3 129.3 129.3 129.3 129.3 194 Fx[3:0] 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 Frame Rate (Hz) 38.8 38.8 38.8 38.8 38.8 48.5 48.5 48.5 48.5 48.5 64.6 64.6 64.6 64.6 64.6 97
The frame rate shown as above is when duty setting is 128. Restriction When duty setting is not 128: Frame rate=default frame rate x (129/(duty setting+1))
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Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Status FA[4:0] Default Power On Sequence S/W Reset H/W Reset 06h 06h 06h
Default Value FB[4:0] 0Bh 0Bh 0Bh FC[4:0] 0Dh 0Dh 0Dh FD[4:0] 12h 12h 12h
Legend
Command
Parameter
Display
Flow Chart
Action
Mode
Sequential transter
Ver. 1.0
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8.1.59 FRM8SEL: Frame Freq. in Temperature range (idle-8 color) (F1H)
NOTE: "-" Don't care
Command FRM8SEL 1 parameter 2 parameter 3 parameter 4 parameter
th rd nd st
A0 0 1 1 1 1
RD 1 1 1 1 1
WR 0 0 0 0 0
D7 1 -
D6 1 -
D5 1 -
D4 1
D3 0
D2 0
D1 0
D0 1
HEX (F1h) Range A Range B
F8A4 F8A3 F8A2 F8A1 F8A0 F8B4 F8B3 F8B2 F8B1 F8B0
F8C4 F8C3 F8C2 F8C1 F8C0 Range C F8D4 F8D3 F8D2 F8D1 F8D0 Range D
Select Frame Freq. in normal display mode.(idle;8 color mode) 1 parameter : Frame freq. value set in TEMP range -40 to TA Description 2 parameter : Frame freq. value set in TEMP range TA to TB 3 parameter : Frame freq. value set in TEMP range TB to TC 4 parameter : Frame freq. value set in TEMP range TC to 87 Restriction
th rd nd st
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes
Status FA[4:0] Default Power On Sequence S/W Reset H/W Reset 06h 06h 06h
Default Value FB[4:0] 0Bh 0Bh 0Bh FC[4:0] 0Dh 0Dh 0Dh FD[4:0] 12h 12h 12h
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Flow Chart
Ver. 1.0
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8.1.60 TMPRNG: Temp. range set for Frame Freq. Adj. (F2H)
NOTE: "-" Don't care
Command TMPRNG 1 parameter 2 parameter 3 parameter
rd nd st
A0 0 1 1 1
RD 1 1 1 1
WR 0 0 0 0
D7 1 -
D6 1 TA6 TB6 TC6
D5 1 TA5 TB5 TC5
D4 1 TA4 TB4 TC4
D3 0 TA3 TB3 TC3
D2 0 TA2 TB2 TC2
D1 1 TA1 TB1 TC1
D0 0 TA0 TB0 TC0
HEX (F2h) Range A Range B Range C
Temp. range set for automatic frame freq. adj. operation according the current temp. value. 1 parameter: Temp. range A value set 2 parameter: Temp. range B value set Description 3 parameter: Temp. range C value set TA/TB/TC Temperature() + 40 = TA/TB/TC[6 :0] Example: If TA wants to be set at 24, TA[6:0]=24+40=64(40h), Restriction -40TATA+THTBTB+THTC87
rd nd st
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes
Status TA[6:0] Default Power On Sequence S/W Reset H/W Reset 1Eh 1Eh 1Eh
Default Value TB[6:0] 28h 28h 28h TC[6:0] 32h 32h 32h
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Flow Chart
Ver. 1.0
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8.1.61 TMPHYS: Temp. Hysteresis Set for Frame Freq. Adj. (F3H) A0 0 1 RD 1 1 WR 0 0 D7 1 D6 1 D5 1 D4 1 D3 0 TH3 D2 0 TH2 D1 1 TH1 D0 1 TH0 HEX (F3h) Command TMPHYS parameter
Temp. hysteresis range set for frame freq. adj. Parameter TH [3:0] is used to set Temp. hysteresis range. The relationship between temp. state and temp. range value is shown below.
TEMP Range Value Freq. changing point A Description Freq. changing point B Freq. changing point C
TEMP Rising State TA[6:0]+TH[3:0] TB[6:0]+TH[3:0] TC[6:0]+TH[3:0]
TEMP Falling State TA[6:0] TB[6:0] TC[6:0]
TH Temperature() - 1 = TH[3:0] Example: If TH wants to set 5, TH [3:0] =5-1=4. Restriction Temp. hysteresis value should be smaller than the gap of temp. range. Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Status Power On Sequence Default S/W Reset H/W Reset
Default Value(TH[3:0]) 02h 02h 02h
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Flow Chart
Ver. 1.0
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8.1.62 TEMPSEL: Temperature Gradient Compensation Coefficient Set (F4H)
NOTE: "-" Don't care
Command TEMPSEL 1 parameter
nd st
A0 /RD 0 1 1 1
/W R 0 0
D7 1
D6 1
D5 1
D4 1
D3 0
D2 1
D1 0
D0 0
Hex (F4h) MT1x: (-24 C to -32 C) MT0x: (-32 C to -40 C) MT3x: (-8 C to -16 C) MT2x: (-16 C to -24 C) MT5x: (8 C to 0 C) MT4x: (0 C to -8 C) MT7x: (24 C to16 C) MT6x: (16 C to 8 C) MT9x: (40 C to 32 C) MT8x: (32 C to 24 C) MTBx: (56 C to 48 C) MTAx: (48 C to 40 C) MTDx: (72 C to 64 C) MTCx: (64 C to 56 C) MTFx: (87 C to 80 C) MTEx: (80 C to 72 C)
o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o
MT13 MT12 MT11 MT10 MT03 MT02 MT01 MT00
2 parameter
rd
1
1
0
MT33 MT32 MT31 MT30 MT23 MT22 MT21 MT20
3 parameter
th
1
1
0
MT53 MT52 MT51 MT50 MT43 MT42 MT41 MT40
4 parameter
th
1
1
0
MT73 MT72 MT71 MT70 MT63 MT62 MT61 MT60
5 parameter
th
1
1
0
MT93 MT92 MT91 MT90 MT83 MT82 MT81 MT80
6 parameter
th
1
1
0
MTB3 MTB2 MTB1 MTB0 MTA3 MTA2 MTA1 MTA0
7 parameter
th
1
1
0
MTD3 MTD2 MTD1 MTD0 MTC3 MTC2 MTC1 MTC0
8 parameter
1
1
0
MTF3 MTF2 MTF1 MTF0 MTE3 MTE2 MTE1 MTE0
Ver. 1.0
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This command defines temperature gradient compensation coefficient. For this command detail description and opearation, please see section7.10.
Parameter n 0 1 2 3 Description : : : 12 13 14 15
MT n 3 0 0 0 0 : : : 1 1 1 1
MT n 2 0 0 0 0 : : : 1 1 1 1
o
MT n 1 0 0 1 1 : : : 0 0 1 1 (+/- 3mv
MT n 0 0 1 0 1 : : : 0 1 0 1 tolerance)
Voltage / C +5 mv / C 0 mv / C -5 mv / C -10 mv / C : : : -55 mv / C -60 mv / C -65 mv / C -70 mv / C
o o o o o o o o
o
Voltage / C Restriction
Please refer to the specification in absolute maximum ratings for operating voltage range. Status Normal Mode On, Idle Mode Off, Sleep Out Yes Yes Yes Yes Yes Availability
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Default Power On Sequence S/W Reset H/W Reset ----
Default Value (MTn[3:0])
Ver. 1.0
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Legend
Command
Parameter
Display
Flow Chart
Action
Mode
Sequential transter
NOTE: The default value of temperature gradient compensation coefficient Set
1 parameter 2
nd rd st
0xFF 0x36 0x04 0x00 0x00 0x42 0xC4 0x59
parameter
3 parameter 4 parameter 5 parameter 6 parameter 7 parameter 8 parameter
th th th th th
Ver. 1.0
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8.1.63 THYS: Temperature detection threshold (F7H)
NOTE: "-" Don't care
Command THYS Parameter
A0 0 1
/RD 1 1
/WR 0 0
D7 1 -
D6 1
D5 1
D4 1
D3 0
D2 1
D1 1
D0 1
Hex (F7h) -
THYS6 THYS5 THYS4 THYS3 THYS2 THYS1 THYS0
Description Restriction
Temperature detection threshold setting.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Yes
Availability
Status Default Power On Sequence S/W Reset H/W Reset 08h 08h 08h
Default Value D[7:0]
Flow Chart
Ver. 1.0
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8.1.64 Frame Set: Frame PWM Set (F9H)
NOTE: "-" Don't care
Command Frame1 Set 1 2
st
A0 0 1 1 : 1 1
/RD 1 1 1 : 1 1
/WR 0 0 0 : 0 0
D7 1 : -
D6 1 : -
D5 1 : -
D4 1 P14 P24 :
D3 1 P13 P23 :
D2 0 P12 P22 :
D1 0 P11 P21 :
D0 1 P10 P20 :
Hex (F9h) -
parameter parameter :
nd
15 16
th th
parameter parameter
P154 P153 P152 P151 P150 P164 P163 P162 P161 P160
Description Restriction
This command is used to set frame PWM.
Status Normal Mode On, Idle Mode Off, Sleep Out Register Availability Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence Default S/W Reset H/W Reset ---Yes Yes Yes Yes Yes
Availability
Default Value
Flow Chart
Ver. 1.0
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NOTE: The default value of RGB level set RGB level0 RGB level1 RGB level2 RGB level3 RGB level4 RGB level5 RGB level6 RGB level7 RGB level8 RGB level9 RGB level10 RGB level11 RGB level12 RGB level13 RGB level14 RGB level15 00H 01H 02H 04H 06H 07H 09H 0AH 0BH 0CH 0DH 0FH 11H 12H 17H 1AH
All the modulation range of each level for each frame is from 00H to 1FH.
Ver. 1.0
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9
9.1
SPECIFICATIONS
Absolute Maximum Ratings
(VSS = 0V) Item Symbol VDD VDD2,VDD3,VDD4,VDD5 VLCD (V0- XV0) VIN TOPR TSTG Value - 0.3 ~ + 3.6 - 0.3 ~ + 3.6 - 0.3 ~ + 18.0 - 0.3 ~ VDD + 0.3 - 30 ~ + 85 - 40 ~ + 125 Unit V V V V C C
Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage range Operating temperature range Storage temperature range
NOTE: (1). Voltages are all based on VSS = 0V.
(2). Voltage relationship: V0 > Vg > Vm > VSS > XV0 must always be satisfied.
Ver. 1.0
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9.2
9.2.1
DC Characteristics
Basic Characteristics (VSS=0V, Ta = -30 to 85 C) Parameter Symbol VDDI VDDA V0 - XV0 IOH = -1.0mA IOL = +1.0mA VIN = VDD or VSS Vg = 2.8V, Ta=25 V0 = 14.0V, Ta=25 Ta=25, *1) S0 to S383 Conditions Related Pins VDD VDD2,3,4,5 V0, XV0 *1) *1) SI, TE
VSS -1.0 1 0.2VDD +1.0 0.7VDD VSS 0.8VDD 18.0
MIN
1.65 2.4
TYP
1.8 2.8
MAX
3.3 3.3
Unit
Logic Operating voltage Analog Operating voltage Driving voltage input High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Driver on resistance (SEG) Driver on resistance (COM)
VLCD VIH VIL VOH VOL IIL RONSEG
V
VDD 0.3VDD VDD
A
K C0 to C127
0.8 -
RONCOM
Frame rate
FR
N-line=0x00, Duty=128, FR=0x12
-
-
77
-
Hz
NOTE: *1) Applies to IF1, IF2, IF3, /CS, /RST, /WR, /RD, A0(SCL) and D15-D2, D1 (A0) ,D0(SI) pins
Ver. 1.0
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9.2.2 Current Consumption (Bare die) Current consumption Operation mode Condition Typical IDD (mA) 1. 1/2 gray pattern Normal Mode 2. Vddi=1.8V, Vdda=2.8V 3. Vop=14V, bias=1/9, n-line=0x00, FR=77Hz, x8 booster, Ta=25 Sleep In Mode
Note: Bare die Note: The current consumption is DC characteristic.
Maximum IDD (mA)
0.6
0.9
Vddi=1.8V, Vdda=2.8V, Ta=25
0.01
0.02
Ver. 1.0
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10
10.1
TIMING CHARACTERISTICS
Parallel Interface Characteristics bus (8080-series MCU)
A0 /CS /WR /RD D[15:0] (Write) D[15:0] (Read)
TAST TCS
TAHT TCSH TCYCR / TCYCW TCCHW
Tr
TCCLW
Tf
TCCLR TDST
TCCHR TDHT
TRAT
TODH
(VSS=0V, VDDI=1.65~3.3V, VDDA=2.4~3.3V, Ta = 25C) Item Address hold time Address setup time Chip select setup time Chip select hold time System cycle time (WRITE) /WR L pulse width (WRITE) /WR H pulse width (WRITE) System cycle time (READ) /RD L pulse width (READ) /RD H pulse width (READ) System cycle time (READ) /RD L pulse width (READ) /RD H pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D15 WR /CS Signal Symbol TAHT TAST TCS TCSH TCYCW TCCLW TCCHW TCYCR RD (ID) TCCLR TCCHR TCYCR RD (FM) TCCLR TCCHR TDS TDH TRAT TODH CL=30pF CL=30pF When read from frame memory 200 200 15 15 -- -- -- -- -- -- 90 80 When read ID data Condition 0 0 10 10 200 80 90 200 80 80 400 Rating Min. A0 Max. -- -- -- -- -- -- -- -- -- -- -- ns Units
*1 The input signal rise time and fall time (Tr, Tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (Tr +Tf) (TCYC8 - TCCLW - TCCHW) for (Tr + Tf) (TCYC8 - TCCLR - TCCHR) are specified.
Ver. 1.0
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*2 All timing is specified using 20% and 80% of VDD as the reference. *3 TCCLW and TCCLR are specified as the overlap between /CS being "L" and WR and RD being at the "L" level.
Ver. 1.0
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10.2 Parallel Interface Characteristics bus (6800-series MCU) A0 R/W /CS
TAST
TCS
TCSH
TAHT
E D[15:0] (Write) D[15:0] (Read)
TEWHW
Tr
TCYCR TCYCW Tf TDHT
TEWLW TEWLR
TEWHR TDST
TRAT
TODH
(VSS=0V, VDDI=1.65~3.3V, VDDA=2.4~3.3V, Ta = 25C) Item Address hold time Address setup time Address hold time Address setup time Chip select setup time Chip select hold time System cycle time (WRITE) Low pulse width (WRITE) High pulse width (WRITE) System cycle time (READ) Low pulse width (READ) High pulse width (READ) System cycle time (READ) Low pulse width (READ) High pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D15 E (FM) E (ID) E /CS R/W Signal Symbol TAHT TAST TAHT TAST TCS TCSH TCYCW TEWLW TEWHW TCYCR TEWLR TEWHR TCYCR TCCLR TCCHR TDS TDH TRAT TODH CL=30pF CL=30pF When read from frame memory 200 200 15 15 -- -- -- -- -- -- 90 80 When read ID data Condition 0 0 10 10 10 10 200 80 60 200 70 80 400 Rating Min. A0 Max. -- -- -- -- -- -- -- -- -- ns -- -- -- -- Units
Ver. 1.0
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10.3 Serial Interface Characteristics (4-pin Serial)
T SAS TSAH
A0
V IH TCHW TCSS VIL TSCYCR / TSCYCW TCSH TCHW
/CS
SCL
I VH VIL
TSLR / TSLW TSDS
TSHR / T SHW T SD H
SI (DIN)
T ACC
TOH
SI (DOUT)
(VSS=0V, VDDI=1.65~3.3V, VDDA=2.4~3.3V, Ta = 25 C) Item Serial clock period (write) SCL "H" pulse width (write) SCL "L" pulse width (write) Serial clock period (read) SCL "H" pulse width (read) SCL "L" pulse width (read) Address setup time Address hold time Data setup time Data hold time Data access time Output disable time Chip select setup time Chip select hold time Chip select "H" pulse width /CS SI A0 SCL Signal Symbol TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSAS TSAH TSDS TSDH TACC TOH TCSS TCSH TCHW CL=30pF CL=30pF Condition 70 35 35 150 70 70 10 10 10 10 -- -- 35 35 0 Rating Min. Max. -- -- -- -- -- -- -- -- -- -- 60 60 -- -- -- ns Units
Ver. 1.0
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10.4 Serial Interface Characteristics (3-pin Serial)
(VSS=0V, VDDI=1.65~3.3V, VDDA=2.4~3.3V, Ta = 25C) Item Serial clock period (write) SCL "H" pulse width (write) SCL "L" pulse width (write) Serial clock period (read) SCL "H" pulse width (read) SCL "L" pulse width (read) Data setup time Data hold time Access time Output disable time Chip select setup time Chip select hold time Chip select "H" pulse width /CS SI SCL Signal Symbol TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSDS TSDH TACC TOH TCSS TCSH TCHW CL=30pF CL=30pF Condition 70 35 35 150 70 70 10 10 -- -- 35 35 0 Rating Min. Max. -- -- -- -- -- -- -- -- 60 60 -- -- -- ns Units
Ver. 1.0
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11 RESET TIMING
/ RST
TRW
Display status
TRT Normal operation During reset Initial condition (Default for H/W reset)
(VSS=0V, Ta = 25C) Item Signal /RST Symbol TRW TRT Condition Min. 10 120 Rating Max. us ms Unit
Reset "L" pulse width Reset time
Ver. 1.0
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12 THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7687A Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7687A series chips with fewer signal lines. The display area can be enlarged by using multiple ST7687A Series chips. When this is done, the chip select signal can be used to select the individual Ics to access. (1) 8080 Series MPUs
(2) 6800 Series MPUs
VDD VCC A0 A0 VDD IF 1 IF 2 IF 3
/CS
D0 to D15 E(/RD) R/W(/WR) /RST GND RESET
/CS
D0 to D15 E (/RD ) R/W (/WR ) /RST VSS
ST7687A
MPU
V SS
(3) Using the Serial Interface (4-line interface)
Ver. 1.0
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(4) Using the Serial Interface (3-line interface)
MPU
Ver. 1.0
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13
13.1
13.1.1
APPLICATION NOTE
Schematic Suggestion
80-8bit parallel interface Mode
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4
1.8V/2.8V 2.4VVDDA3.3V HHL H (internal OSC) L 1uF/16V 1uF/25V 1uF/16V 1uF/16V (Optional)
FPC Interface
FPC
ITO
A0 WR D0 D1 D2 D3 D4 D5 D6 D7 RD /RST /CS VDDI
C4
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
EXT (Test point)
VSS
VSS VSS 2
61 62
VDDA
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
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13.1.2 80-16bit parallel interlace Mode
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4
1.8V/2.8V 2.4VVDDA3.3V HHH H (internal OSC) L 1uF/16V 1uF/25V 1uF/16V 1uF/16V (Optional)
FPC Interface
A0 WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
RD
FPC
ITO
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
EXT (Test point)
/RST /CS VDDI
VSS
VSS VSS 2
61 62
C4
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDDA
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
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13.1.3 68-8bit parallel interlace Mode
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4
1.8V/2.8V 2.4VVDDA3.3V HLL H (internal OSC) L 1uF/16V 1uF/25V 1uF/16V 1uF/16V (Optional)
FPC Interface
FPC
ITO
673
661
A0 RW D0 D1 D2 D3 D4 D5 D6 D7 E /RST /CS VDDI
C4
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
COM 24
COM 0
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
EXT (Test point)
Gold bump face up
...
VSS
...
VSS VSS 2
61 62
VDDA
...
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 COM 1 148 COM 25
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
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13.1.4 68-16bit parallel interlace Mode
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4
1.8V/2.8V 2.4VVDDA3.3V HLH H (internal OSC) L 1uF/16V 1uF/25V 1uF/16V 1uF/16V (Optional)
FPC Interface
A0 RW D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
E
FPC
ITO
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
EXT (Test point)
/RST /CS VDDI
VSS
VSS VSS 2
61 62
C4
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDDA
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
176/191
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13.1.5 3-line serial interlace Mode
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4
1.8V/2.8V 2.4VVDDA3.3V LHL H (internal OSC) L 1uF/16V 1uF/25V 1uF/16V 1uF/16V (optional)
FPC Interface
FPC
ITO
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
SCL SI
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
RST /CS VDDI
C4 EXT (Test point)
VSS
VSS VSS 2
61 62
VDDA
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
177/191
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13.1.6 4-line serial interlace Mode
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4
1.8V/2.8V 2.4VVDDA3.3V LHH H (internal OSC) L 1uF/16V 1uF/25V 1uF/16V 1uF/16V (optional)
FPC Interface
FPC
ITO
673
661
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
COM 24
COM 0
SCL SI A0
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
RST /CS VDDI
C4 EXT (Test point)
Gold bump face up
...
VSS
...
VSS VSS 2
61 62
VDDA
...
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 COM 1 148 COM 25
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
178/191
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13.1.7 80-8bit parallel interlace Mode while typical Vddi=3V/3.3V
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4 R1
3V/3.3V 2.4VVDDA3.3V HHL H (internal OSC) H 1uF/16V 1uF/25V 1uF/16V 1uF/16V 1M
FPC Interface
FPC
ITO
A0 WR D0 D1 D2 D3 D4 D5 D6 D7 RD /RST /CS VDDI
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
EXT (Test point) R1 C4
VSS
VSS VSS 2
61 62
VDDA
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
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13.1.8 4-line serial interlace Mode while typical Vddi=3V/3.3V
Typical VDDI VDDA IF[3:1] CLS INTVD1 C1 C2 C3 C4 R1
3V/3.3V 2.4VVDDA3.3V LHH H (internal OSC) H 1uF/16V 1uF/25V 1uF/16V 1uF/16V 1M
FPC Interface
FPC
ITO
673
661
VPP (Test point)
VSS VPP VPP VPP VPP CL CLS VSS VDD INTVD1 A0 VDD RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RW_WR A0 /RST IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VD1in VD1in VD1in VD1in VD1out VD1out VSS1 VSS1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
660
COM 26
COM 24
COM 0
SCL SI A0
610 609
COM 126 DUMMY
597
DUMMY
596 595
SEG383 SEG382
RST /CS VDDI
R1 C4 EXT (Test point)
Gold bump face up
...
VSS
...
VSS VSS 2
61 62
VDDA
...
VSS 2 VSS 4 VSS 4 VSS 4 VREF VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VDD2 VSS2
93 94
C3
C2 C1
VSS2 Vm Vm Vm Vm Vm Vm V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0s XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 COM 1 148 COM 25
214 213
SEG1 SEG0
212
DUMMY
200 199
DUMMY COM 127
149
COM 27
Ver. 1.0
180/191
2009/12
ST7687A
13.2 Power on flow and sequence:
Power On Keeping the /RES Pin = "L" and waiting for stabilizing the Power /RES Pin="H" and wait a minute ( tR > 120ms ) Initial LCM display off sleep out Vop setting booster control function setting write DDRAM Display on
Normal operating TrTW
TrTW >=0
VDDI
(Digital)
VDDA
(Analog)
tRW
/RES
tRW > 10 us
Internal State Power On Reset Initial LCM
TrTW
TrTW >=0
VDDI
(Digital)
VDDA
(Analog)
/RES
tRW
tRW > 10 us
Internal State Power On Reset Initial LCM
Ver. 1.0
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ST7687A
13.3 Power off flow and sequence
Normal operating
Keeping /RES pin="L" Wait power turning off (tR>120ms)
Turn off power (Vdd & Vdd2) Power off
tfPW
VDDI
(Digital)
tfPW >=0
VDDA
(Analog)
tpfall
/RES tR Internal State Normal operating Reset
tR=120ms
Power Off
Keep the /RES = Low
Note: 1. When turning VDDA OFF, the falling time should follow the specification: tPfall 300msec 2. If the power off flow cannot meet this specification, it's recommend to use the resistor shown as blow.
Ver. 1.0
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ST7687A
13.4 PROM Burning Flow:
Power on
HW Reset Delay 120ms Push into program flow Initial LCD Module for checking performance void INITIAL_7687A (void) Key P Show image and fine tune Vop void Fine_Tune_Vop(void)
Key
+ Adjustment
/EXT connect to VSS
VPP connect to 6.5V
PROM write void PROMwrite_7687A (void)
Remove 6.5V from VPP
Remove VSS from /EXT
HW reset Delay 120ms Initial LCD Module for checking performance void INITIAL_7687A (void)
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13.5 Software coding flow
void INITIAL_7687A (void) { //-----------------------------Disable Auto read ------------------------------------// Write(COMMAND,0xD7); Write(DATA,0x9F); // Disable auto read
//-----------------------------Read Data From PROM------------------------// Write(COMMAND,0xe0); Write(DATA,0x00); delayms(200); Write(COMMAND,0xe3); delayms(200); Write(COMMAND,0xe1); // Delay 200ms // Read from PROM // Delay 200ms // PORM control out // PROM control in
//---------------------------------- Sleep OUT ---------------------------------------// Write(COMMAND, 0x28 ); Write(COMMAND, 0x11 ); delayms(250); // Display off // Sleep Out // Delay 250ms
//--------------------------------Vop Setting------------------------------------------// Write(COMMAND,0xc0); Write(DATA, 0x12); Write(DATA, 0x01); //--------------------------------Set Write(COMMAND,0xc3); Write(DATA,0x04); Write(COMMAND,0xc4); Write(DATA,0x07); Write(COMMAND,0xcb); Write(DATA,0x01); Write(COMMAND,0x36); Write(DATA,0x80); Write(COMMAND,0xb5); Write(DATA,0x04); Write(COMMAND,0xbd); Write(DATA,0x04); Write(COMMAND,0xd0); //Vop setting //Vop = 14.56V // base on Module Register---------------------------------------// // Bias selection // 1/8 Bias // Booster setting // Booster X 8 // Vg source control // Vg from 2xVdda // Memory data access control // // N-line Setting // // CrossTalk compensation setting // // Analog circuit setting
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ST7687A
Write(DATA,0x1D); Write(COMMAND,0x25); Write(DATA,0x3F); Write(COMMAND,0x3A); Write(DATA,0x05); Write(COMMAND,0xb0); Write(DATA,0x7F); Write(COMMAND,0x2A); Write(DATA,0x00); Write(DATA,0x7F); Write(COMMAND,0x2B); Write(DATA,0x00); Write(DATA,0x7F); // Row address setting // 0~127 // // Write Contrast // // Interface Pixel Format //16bits/pixel //Display Duty Setting // Duty = 128 duty // Column address setting // 0~127
void gamma (void); void TC_setting (void);
Write(COMMAND,0x29); }
// Display On
//--------------------------------------Set void gamma (void) { Write(COMMAND,0xf9); Write(DATA,0x00); Write(DATA,0x02); Write(DATA,0x04); Write(DATA,0x06); Write(DATA,0x08); Write(DATA,0x0A); Write(DATA,0x0C); Write(DATA,0x0E); Write(DATA,0x10); Write(DATA,0x12); Write(DATA,0x14); Write(DATA,0x16); Write(DATA,0x18); Write(DATA,0x1A);
Gamma------------------------------------------//
// Set frame RGB value
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Write(DATA,0x1C); Write(DATA,0x1E); }
//---------------------------------TC setting--------------------------------------// void TC_setting (void) { Write(COMMAND,0xf4); Write(DATA,0xff); Write(DATA,0x49); Write(DATA,0x23); Write(DATA,0x02); Write(DATA,0x00); Write(DATA,0x42); Write(DATA,0x75); Write(DATA,0x87); } //TC setting
void Fine_Tune_Vop(void) { //------------------------------------- Show Map ----------------------------------------------Show_Image(); //Display a image
//------------------------------------ Display ON ----------------------------------------------Write(COMMAND, 0x29 ); // Display On
//--------------------------------Fine tune Vop offset---------------------------------------Write( COMMAND, 0xc1); or Write( COMMAND, 0xc2); } //Fine tuning Vop here by command 0xc1 (VopOffsetInc), 0xc2 (VopOffsetDec).
void PROMwrite_7687A (void) { //--------------------------------------display off------------------------------------// Write(COMMAND,0x28); delayms(50); // Display off // Delay 50ms
//--------------------------------------PROM write mode--------------------------------// Write(COMMAND,0xf0); // Frame Freq. in Temp range A,B,C and D
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ST7687A
Write(DATA, 0x12); Write(DATA, 0x12); Write(DATA, 0x12); Write(DATA, 0x12);
Write(COMMAND,0xe4); Write(DATA, 0x58); Write(COMMAND,0xe5); Write(DATA, 0x0F); Write(COMMAND,0xe0); Write(DATA, 0x20); delayms(100);
// SELPROM
// Programmable rom setting
//PROM control in
//Delay 100ms
Write(COMMAND,0xe2); delayms(250);
// Write to PROM //delay 250ms
Write(COMMAND,0xe1); }
Note:
//PROM control out
#1 If the Vop and display performance is not suitable after burning PROMthe Vop has to fine tune again. #2 In this section"+" & "-" key button, please execute Write(COMMAND,0xC1) to increase one step at Vop and execute Write(COMMAND,0xC2) to decrease one step at Vop, if necessary. #3 The TC is turn on in burning flow. If LCD module is too dark or bright, it's an effect of backlight.
Ver. 1.0
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ST7687A
13.6 Timing sequence of each power level in initial and program flow:
Note: #1 VPP pad can have 6.5V only when Vddi and Vdda have power. #2 Reset signal can not be low level in program period.
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2009/12
ST7687A
13.7 Suggestion circuit:
Note: #1 In order to accomplish VPP pad have 6.5v only when vddi and vdda have power and /ext pad connect to vss in programming period, the PROM programming system suggestion is shown above that use relay controlled by mcu to achieve controlling VPP and /ext power level by software.
Ver. 1.0
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2009/12
ST7687A
13.8 ESD Protection: For ESD protection of the LCM, here are some recommendations:
1.
RST (Reset pin): Please increase the resistance of this pin.
IC Side
IF1
R
ITO
/RST
A0
2.
ESD Protection Ring: "Shielding Ground" is the first protection of ESD. By connecting
the "Blue" (ITO) ring to the FPC, the protection ring is finished.
Ver. 1.0
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ST7687A
14 REVISION HISTORY
ST7687A Serial Specification Revision History
Version 1.0 Date 2009/12 First Issue Description
Ver. 1.0
191/191
2009/12

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